Fan-out WLP - The enabler for system-in-package on Wafer Level (WLSIP)

2012 4th Electronic System-Integration Technology Conference, ESTC 2012

Volumn , Issue , 2012, Pages

  Kröhnert, Steffen ^a   Campos, José ^b   O'Toole, Eoin ^b  

^a NANIUM SA Branch Office Dresden   (Germany)

^b NANIUM SA   (Portugal)

Author keywords

1L RDL; 2L RDL; EWLB; Fan out wafer level packaging; FO WLP; MCM; MCP; SiP; Solder ball pitch; Stacking; WLP; WLSiP

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BATCH DATA PROCESSING; CHIP SCALE PACKAGES; ELECTRONICS ENGINEERING; INTEGRATION; MULTICARRIER MODULATION; SYSTEM-IN-PACKAGE; SYSTEM-ON-CHIP; TECHNOLOGY;

1L-RDL; 2L-RDL; EWLB; FO-WLP; MCP; SIP; SOLDER BALLS; STACKING; WAFER LEVEL PACKAGING; WLP; WLSIP;

PACKAGING;

EID: 84902477935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2012.6542153     Document Type: Conference Paper

References (3)

1. T. Meyer, G. Ofner, S. Bradl, M. Brunnbauer, R. Hagen: "Embedded Wafer Level Ball Grid Array (eWLB)", 2008, 10th Electronics Packaging Technology Conference (ECTC)
2. Yonggang Jin, et al, "Next Generation eWLB (embedded Wafer Level BGA) Packaging", 2010, 12th Electronics Packaging Technology Conference (ECTC)
3. Rao R. Tummala, Madhavan Swaminathan: "Introduction to System-on-Package (SOP), Minaturization of the Entire System", 2007, McGraw-Hill