An analog CMOS neural network with on-chip learning and multilevel weight storage

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1112 LNCS, Issue , 1996, Pages 761-766

  Conti, M ^a   Guaitini, G ^a   Turchetti, C ^a  

^a UNIVERSITÀ POLITECNICA DELLE MARCHE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

ANALOG CMOS; ANALOG NEURAL NETWORK; AREA-EFFICIENT; CIRCUIT SOLUTION; ON-CHIP LEARNING; METAL PROCESS; SILICON AREA;

NEURAL NETWORKS;

EID: 84902131675     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61510-5_128     Document Type: Conference Paper

References (8)

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4. Y.K.Choi, S.Y.Lee, "Subthreshold MOS Implementation of Neural Networks with On-Chip Error Back-Propagation Learning", Proc. of I.J.C.N.N., 1993, pp. 849-852.
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6. A.Papoulis, "Probability, random variables, and stochastic processes", McGraw- Hill, New York, 1965.
7. M.Conti, S.Orcioni, C.Turchetti, "A Class of Neural Networks Based on Approximate Identity for Analog IC's Implementation", IEICE Trans. on Fundamentals, Japan, Vol. 77, No. 6, June 1994, pp. 1069-1079.
8. M.H.Cohen, A.G.Andreou, "Current-Mode Subthreshold MOS Implementation of the Herault-Jutten Autoadaptive Network", IEEE J. Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 714-727.