A FPGA-based bit-word PLC CPUs development platform

IFAC Proceedings Volumes (IFAC-PapersOnline)

Volumn 10, Issue PART 1, 2010, Pages 132-137

  Chmiel, Miroslaw ^a   Mocha, Jan ^a   Hrynkiewicz, Edward ^a  

^a SILESIAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Bit byte (word) structure of CPU; Central processing unit; Concurrent operation; Field programmable gate array; Programmable logic controller; Scan time; Throughput time

Indexed keywords

COMPUTER CIRCUITS; CONCURRENCY CONTROL; CONTROLLERS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE CODING; PROGRAM PROCESSORS; PROGRAMMED CONTROL SYSTEMS; SOFTWARE TESTING;

CONCURRENT OPERATIONS; DEVELOPMENT PLATFORM; DUAL PROCESSORS; HARDWARE SOLUTIONS; SCAN TIME; SOFTWARE PLATFORMS; THROUGHPUT TIME; TWO PROCESSORS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 84901912713     PISSN: 14746670     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.3182/20101006-2-pl-4019.00026     Document Type: Conference Paper

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