A quick parasitics extraction tool for IC interconnections

Progress in Electromagnetics Research Symposium

Volumn , Issue , 2006, Pages 173-177

  Yang, Yang ^a   Wang, Gaofeng ^a   Xue, Jintao ^b  

^a WUHAN UNIVERSITY   (China)

^b FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; EXTRACTION;

GENERALIZED MINIMAL RESIDUAL ALGORITHMS; IC INTERCONNECTIONS; INTERCONNECT PARASITIC RESISTANCE; NUMERICAL TECHNIQUES; PARALLEL CAPACITANCE; PIECE-WISE CONSTANTS; SPECIAL APPLICATIONS; THREEDIMENSIONAL (3-D);

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84901710109     PISSN: 15599450     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Q. K. Zhu, Interconnect RC and Layout Extraction for VLSI, Canada: Trafford Publishing, 2002.
2. K. Nabors, J. White, "Multipole-accelerated capacitance extraction algorithms for 3-D structures with multiple dielectrics," IEEE Trans. Circuit and Systems-1: Fundamental Theory and Applications, Vol. 39, pp. 946-954, 1992.
3. Y. Saad, M. H. Schultz, "GMRES: A generalized minimal residual algorithm for solving nonsymmetric linear systems," SIAM J. Scientific and Statistical Computing, Vol. 7, pp. 856-869, 1986.
4. L. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: MIT Press, 1988.
5. C. Wei, R. F. Harrington, J. R. Mautz, T. K. Sarkar, "Multiconductor transmission lines in multilayered dielectric media," IEEE Trans. Microwave Theory and Techniques, Vol. 32, pp. 439-450, 1984.
6. G. W. Pan, G. Wang, B. K. Gilbert, "Edgy effect enforced boundary analysis of multilayered transmission lines," IEEE Trans. Circuits and Systems-1: Fundamental Theory and Applications, Vol. 39, pp. 955-963, 1992.
7. M. Bächtold, M. Spasojevic, C. Lage and P. B. Ljung. "A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, pp. 325-338, 2000.
8. F. Yu and W. Shi, "A divide-and-conquer algorithm for 3D capacitance extraction," ISQED 2004, pp. 253-258, 2004
9. C. A. Desoer and E. S. Kuh, Basic Circuit Theory. New York: McGraw-Hill, 1969.
10. K. Nabors, J. White, "Fastcap: A multipole accelerated 3-D capacitance extraction program," IEEE Trans. Computer - Aided Design of Integrated Circuit and System, Vol. 10, pp. 1447-1459, 1991.