Measuring memory hierarchy performance of cache-coherent multiprocessors using micro benchmarks

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 1997, Pages

  Hristea, Cristina ^a   Lenoski, Daniel ^b   Keen, John ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BENCHMARKING; COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS;

BENCHMARK SUITES; COHERENCE EFFECTS; COMMERCIAL APPLICATIONS; MEMORY BOTTLENECK; MEMORY CONTENTIONS; MEMORY HIERARCHY PERFORMANCE; MEMORY PERFORMANCE; SHARED MEMORY MULTIPROCESSOR;

CACHE MEMORY;

EID: 84900343434     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/509593.509638     Document Type: Conference Paper

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