New three dimensional (3D) memory array architecture for future ultra high density DRAM (invited)

ICCDCS 2002 - 4th IEEE International Caracas Conference on Devices, Circuits and Systems

Volumn , Issue , 2002, Pages

  Masuoka, F ^a   Endoh, T ^a   Sakuraba, H ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

THREE DIMENSIONAL;

BIT CELL; BIT LINES; BITLINE CAPACITANCE; DESIGN RULES; PROPOSED ARCHITECTURES; THREE-DIMENSIONAL (3D) MEMORY; TWO DIMENSIONAL (2D) ARRAYS; ULTRAHIGH DENSITY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84900336979     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCDCS.2002.1004003     Document Type: Conference Paper

References (3)

1. J K. Sunouchi et al, IEDM Tech. Dig., p.23, 1989
2. H.Takato et al, IEEE Tran. ED ~0138p, .573, 1991.
3. T. Hasegawa et al, IEEE J. SC 01.28, p1099, 1993