A multi-level optimization method for stencil computation on the domain that is bigger than memory capacity of GPU

Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013

Volumn , Issue , 2013, Pages 1080-1087

  Jin, Guanghao ^a   Endo, Toshio ^a   Matsuoka, Satoshi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

GPU memory capacity; multi level optimization; stencil computation; temporal blocking

Indexed keywords

DISTRIBUTED COMPUTER SYSTEMS; PROBLEM SOLVING;

2 LAYER; MEMORY ACCESS; MEMORY CAPACITY; MULTILEVEL OPTIMIZATION; PROBLEM SIZE; STENCIL COMPUTATIONS; TEMPORAL BLOCKING;

GRAPHICS PROCESSING UNIT;

EID: 84899705665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2013.58     Document Type: Conference Paper

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