Low-power, Low-storage-overhead chipkill correct via Multi-line error correction

International Conference for High Performance Computing, Networking, Storage and Analysis, SC

Volumn , Issue , 2013, Pages

  Jian, Xun ^a   Duwe, Henry ^a   Sartori, John ^b   Sridharan, Vilas ^c   Kumar, Rakesh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION;

CHIPKILL; CODEWORD; ERROR DETECTION AND CORRECTION; HIGH POWER; LOW POWER; MEMORY CAPACITY; MEMORY ERROR; STORAGE OVERHEAD;

COST REDUCTION;

EID: 84899670484     PISSN: 21674329     EISSN: 21674337     Source Type: Conference Proceeding    
DOI: 10.1145/2503210.2503243     Document Type: Conference Paper

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