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Volumn 18, Issue 3, 2014, Pages 507-510

Mitigation of asymmetric link delays in IEEE 1588 clock synchronization systems

Author keywords

asymmetry; clock synchronization; IEEE 1588

Indexed keywords

MECHANICAL CLOCKS; SYNCHRONIZATION;

EID: 84899089524     PISSN: 10897798     EISSN: None     Source Type: Journal    
DOI: 10.1109/LCOMM.2014.012214.132540     Document Type: Article
Times cited : (27)

References (10)
  • 3
    • 79958247985 scopus 로고    scopus 로고
    • Fundamental limits on synchronizingclocks over networks
    • Jun.
    • N. Freris, S. Graham, and P. Kumar, "Fundamental limits on synchronizingclocks over networks," IEEE Trans. Automatic Control, vol. 56,no. 6, pp. 1352-1364, Jun. 2011.
    • (2011) IEEE Trans. Automatic Control , vol.56 , Issue.6 , pp. 1352-1364
    • Freris, N.1    Graham, S.2    Kumar, P.3
  • 7
    • 80052071803 scopus 로고    scopus 로고
    • An enhanced end-to-end transparent clockmechanism with a fixed delay ratio
    • Aug.
    • Z. Du, Y. Lu, and Y. Ji, "An enhanced end-to-end transparent clockmechanism with a fixed delay ratio," IEEE Commun. Lett., vol. 15,no. 8, pp. 872-874, Aug. 2011.
    • (2011) IEEE Commun. Lett. , vol.15 , Issue.8 , pp. 872-874
    • Du, Z.1    Lu, Y.2    Ji, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.