An adaptive WTA using floating gate technology

Advances in Neural Information Processing Systems

Volumn , Issue , 1997, Pages 720-726

  Kruger, W Fritz ^a   Hasler, Paul ^a   Minch, Bradley A ^a   Koch, Christof ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING GATE TECHNOLOGY; FLOATING GATE TRANSISTORS; SIMPLIFIED ANALYSIS; STANDARD CMOS; TIME DIMENSION; WINNER-TAKE-ALL CIRCUITS;

EID: 84899007253     PISSN: 10495258     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and CA. Mead "Winner-Take-All Networks of 0(N) Complexity", NIPS 1 Morgan Kaufmann Publishers, San Mateo, CA, 1989, pp 703-711.
2. Grossberg S. "Adaptive Pattern Classification and Universal Recoding: I. Parallel Development and Coding of Neural Feature Detectors." Biological Cybernetics vol. 23, 121-134, 1988.
3. P. Hasler, C. Diorio, B. A. Minch, and C. Mead, "Single Transistor Learning Synapses", NIPS 7, MIT Press, 1995, 817-824. Also at http://www.pcmp.caltech.edu /anaprose/paul.
4. P. Hasler, B. A. Minch, C. Diorio, and C. Mead, "An autozeroing amplifier using pFET Hot-Electron Injection", ISC AS, Atlanta, 1996, III-325-III-328. Also at http://www.pcmp.caltech.edu/anaprose/paul.
5. M. Lenzlinger and E. H. Snow (1969), "Fowler-Nordheim tunneling into thermally grown Si02" J. Appl. Phys., vol. 40, pp. 278-283, 1969.