10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 188-189

  Noethen, Benedikt ^a   Arnold, Oliver ^a   Adeva, Esther Pérez ^a   Seifert, Tobias ^a   Fischer, Erik ^a   Kunze, Steffen ^a   Matúš, Emil ^a   Fettweis, Gerhard ^a   Eisenreich, Holger ^a   Ellguth, Georg ^a   Hartmann, Stephan ^a   Höppner, Sebastian ^a   Schiefer, Stefan ^a   Schlüßler, Jens Uwe ^a   Scholze, Stefan ^a   Walter, Dennis ^a   Schüffny, René ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION REQUIREMENTS; APPLICATION-SPECIFIC HARDWARE; DEGREE OF FLEXIBILITY; GENERAL PURPOSE PROCESSORS; HIERARCHICAL POWER MANAGEMENT; ITERATIVE DETECTION-DECODING; PERFORMANCE REQUIREMENTS; PROCESSING PERFORMANCE;

APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; GENERAL PURPOSE COMPUTERS; ITERATIVE DECODING; MULTIPROCESSING SYSTEMS; RADIO BROADCASTING; SCHEDULING; WIRELESS TELECOMMUNICATION SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 84898079313     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757394     Document Type: Conference Paper

References (7)

1. F. Clermidy, et al., "A 477mW NoC-based digital baseband for MIMO 4G SDR," ISSCC Dig. Tech. Papers, pp. 278-279, 2010.
2. D. llitzky, et al., "Architecture of the Scalable Communications Core's Network on Chip," IEEE Micro, vol. 27, no. 5, pp. 62-74, 2007.
3. T. Limberg, et al., "A Fully Programmable 40 GOPS SDR Single Chip Baseband for LTE/WiMax Terminals", European Solid-State Circuits Conf., pp. 466-469, 2008.
4. D. Walter, et al., "A Source-Synchronous 90Gb/s Capacitively Driven Serial On-Chip Link Over 6mm in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 180-181, 2012.
5. E. P. Adeva, et al., "VLSI Architecture for MIMO Soft-lnput Soft-Output Sphere Detection", J. of Signal Processing Systems, vol. 70, is. 2, pp. 125-143, 2013.
6. 2 65nm CMOS Flexible MIMO Detection-Decoding Engine Achieving 4G Wireless Data Rates," ISSCC Dig. Tech. Papers, pp. 216-218, 2012.
7. O. Arnold, et al., "Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit", IEEE Symp. VLSI Circuits, pp. 249-254, 2012.