Investigation of different methods for isolation in through silicon via for 3D integration

Microelectronic Engineering

Volumn 107, Issue , 2013, Pages 61-64

  Sage, Stéphane ^a   John, Peggy ^b   Dobritz, Stephan ^b   Börnge, Jochen ^a   Vitiello, Julien ^a   Böttcher, Matthias ^b  

^a Altatech   (France)

^b Fraunhofer Institute Reliability and Microintegration   (Germany)

Author keywords

Conformality; HPCVD; Liner; PECVD; TSV

Indexed keywords

ASPECT RATIO; CHEMICAL VAPOR DEPOSITION; DEPOSITION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON OXIDES; VAPOR DEPOSITION;

CHEMICAL VAPOUR DEPOSITION; CONFORMALITY; CU DIFFUSION BARRIER; HPCVD; LINER; REDUCED POWER CONSUMPTION; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84897969794     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2012.11.027     Document Type: Article

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