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Volumn , Issue , 2001, Pages

The choice of cell size and the use of pre-calculated correction factors in the analysis of planar circuits using FDTD and TLM

Author keywords

[No Author keywords available]

Indexed keywords

CELL SIZE; CORRECTION FACTORS; PLANAR CIRCUIT; TLM METHOD;

EID: 84897544335     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMA.2001.339157     Document Type: Conference Paper
Times cited : (5)

References (1)
  • 1
    • 0034427617 scopus 로고    scopus 로고
    • The inclusion of fringing capacitance and inductance in fdtd for the robust accurate treatment of material discontinuities
    • December
    • C. J. Railton, "The Inclusion of Fringing Capacitance and Inductance in FDTD for the Robust Accurate Treatment of Material Discontinuities", IEEE Trans MTT-48, December 2000, pp. 2283-2288
    • (2000) IEEE Trans MTT-48 , pp. 2283-2288
    • Railton, C.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.