Sub-micron CMOS characterisation for single chip wireless applications

2001 31st European Microwave Conference, EuMC 2001

Volumn , Issue , 2001, Pages

  Toner, B ^a   Fusco, V F ^a   Alam, M S ^a   Armstrong, G A ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC LOADS; MEASUREMENTS; SCATTERING PARAMETERS; WIRELESS TELECOMMUNICATION SYSTEMS;

CMOS TRANSISTORS; HARMONIC RESPONSE; LOAD-PULL MEASUREMENT; MEASUREMENT SYSTEM; MODEL VALIDATION; OPTIMAL CIRCUIT DESIGNS; VALIDATION DATA; WIRELESS APPLICATION;

CMOS INTEGRATED CIRCUITS;

EID: 84897505268     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMA.2001.339184     Document Type: Conference Paper

References (4)

1. X. Jin et al., "An effective gate resistance model for CMOS RF and Noise modelling," in IEDM Tech. Dig. 1998
2. M. S. Alam, G. A. Armstrong, B. Toner and V. F. Fusco, "RF Model for Deep-Submicron CMOS," in Proc. ICCCD-2000, Dec. 2000, pp. 159-162.
3. D. Rytting, "Network Analyzer Error Models and Calibration Methods," HP Appl. Note.
4. W. Li, MOSFET models for SPICE simulation, including BSIM3v3 and BSIM4, NY, Wiley, 2001.