A manufacturing system simulation of semiconductor packaging substrate

Spring Simulation Multiconference 2009 - Co-located with the 2009 SISO Spring Simulation Interoperability Workshop

Volumn , Issue , 2009, Pages

  Moon, Dug Hee ^a   Shin, Kyeong Wook ^a   Park, Chul Soon ^a   Kim, Dong Soo ^a  

^a Changwon National University   (South Korea)

Author keywords

Discrete event simulation; Lead frame; Manufacturing system design; Packaging substrate; Semiconductor

Indexed keywords

CHIP SCALE PACKAGES; DISCRETE EVENT SIMULATION; ELECTRONICS PACKAGING; INVESTMENTS; MANUFACTURE; PACKAGING; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR MATERIALS;

BUSINESS ENVIRONMENTS; LEAD FRAME; MANUFACTURING SYSTEM SIMULATIONS; PACKAGING SUBSTRATES; PARALLEL MANUFACTURING SYSTEMS; PRODUCTION ENVIRONMENTS; SEMICONDUCTOR INDUSTRY; SEMICONDUCTOR PACKAGING;

SUBSTRATES;

EID: 84897111030     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Ertay T., Ruan D. and Tuzkaya U. (2006), "Integrating Data Envelopment Analysis and Analytic Hierarchy for the Facility Layout Design in Manufacturing Systems", Information Sciences, Vol. 176, pp. 237-262.
2. Delmia Corp. (2002), QUEST User Manual, Troy, U. S. A.
3. Finch, Byron J. (2006), Operations Now: Profitability, Processes, Performance. 2nd ed. Boston: McGraw-Hill/Irwin.
4. Kelton D., Sadowski R. and Sadowski D. (2002), Simulation with ARENA, 2nd ed, McGraw-Hill, U. S. A.
5. http://www. samsungtechwin. com/
6. http://www. siliconfareast. com/leadframes. htm