Optics for high-performance servers and supercomputers

Optics InfoBase Conference Papers

Volumn , Issue , 2010, Pages

  Benner, Alan F ^a   Kuchta, Daniel M ^b   Pepeljugoski, Petar K ^b   Budd, Russell A ^b   Hougham, Gareth ^b   Fasano, Benjamin V ^a   Marston, Kenneth ^a   Bagheri, Harry ^a   Seminaro, Edward J ^a   Xu, Hui ^c   Meadowcroft, David ^c   Fields, Mitchell H ^c   McColloch, Larry ^c   Robinson, Michael ^c   Miller, Frederick W ^c   Kaneshiro, Ron ^c   Granger, Russell ^d   Childers, Darrell ^d   Childers, Eric ^d  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c BROADCOM CORPORATION   (United States)

^d US Conec Ltd   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CPU CORES; LOW-LATENCY; OPTICAL INTERCONNECT;

SUPERCOMPUTERS;

EID: 84896847534     PISSN: None     EISSN: 21622701     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. D. Grice, et. al., "Breaking the Petaflops Barrier", IBM J. of Research and Development, Vol. 53, No. 5, pp. 1:1-1:15, (2009).
2. A. Benner, "Cost-effective optics: Enabling the Exascale Roadmap", presented at Hot Interconnects 17, August 2009.
3. http://www.darpa.mil/IPTO/programs/hpcs/hpcs.asp
4. R. Kalla B. Sinharoy, "POWER7TM: IBM's Next Generation POWER Microprocessor", presented at Hot Chips 21, August 2009.
5. W. Starke, "POWER7TM: IBM's Next Generation, Balanced POWER Server Chip", presented at Hot Chips 21, August 2009.