Networks on chips

Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years Date

Volumn , Issue , 2008, Pages 105-110

  De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84895297716     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4020-6488-3_8     Document Type: Chapter

References (14)

1. G. De Micheli and L. Benini, Networks on Chips, Morgan Kaufmann, 2006.
2. W. Dally and C. Seitz, The Torus Routing Chip, Distributed Processing, Vo l 1, pp. 187-196, 1996.
3. W. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, Proceedings of the 38th Design Automation Conference, pp. 684-689, 2001
4. M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi and L. Benini, Xpipes: A Latency. Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs, International Conference on Computer Design, pp. 536-539, 2003.
5. P. Guerrier and A. Greiner, A Generic Architecture for On-Chip Packet-Switched Interconnections, DATE-Proceedings of the Design Automation and Test in Europe Conference, pp. 250-256, 2000.
6. J. Hu and R. Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, DATE-Proceedings of the Design and Test Europe Conference, pp. 10688-10693, 2003.
7. A. Jalabert, S. Murali, L. Benini and G. De Micheli, xpipesCompiler: a tool for instantiating application specific Networks on Chips, DATE-Proceedings of the Design and Test Europe Conference, pp. 884-889, 2004.
8. S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparsø and J. Madsen, A Network Traffic Generator Model for fast Network on-Chip Simulation, DATE-Proceedings of the Design and Test Europe Conference, pp. 780-785, 2005.
9. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli and L. Raffo, Designing Application-specific Networks on Chips with Floorplan Information, International Conference on Computer Aided Design, pp. 355-362, 2006.
10. M. Oka and M. Suzuoki, Designing and Programming the Emotion Engine, IEEE Micro, Vol. 19, No. 6, 20-28, Nov.-Dec, 1999.
11. A. Pullini, F. Angiolini, P. Meloni, D. Atienza, S. Murali, L. Raffo, G. De Micheli and L. Benini, NoC Design and Implementation in 65nm Technology, International Symposium on Networks on Chips, pp. 273-282, 2007.
12. E. Rijpkema, K. Goossens, A. Rdulescu, J. Dielissen, J. Van Meerbergen, P. Wielage and E. Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best Effort Services for Networks on Chips, DATE-Proceedings of the Design and Test Europe Conference, pp. 10350-10355, 2003
13. T. Theis, The future of Interconnection Technology, IBM Journal of Research and Development, Vol. 44, No. 3, 379-390, May 2000.
14. S. Vangal et al., An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. International Solid-State Circuits Conference, pp. 98-99, 2007.