Self-Aligned UMOSFET's with a Specific On-Resistance of 1 mΩ · cm2

IEEE Transactions on Electron Devices

Volumn 34, Issue 11, 1987, Pages 2329-2334

  Chang, H R ^a   Black, R D ^a   Temple, V A K ^a   Tantraporn, Wirojana ^a   Baliga, B Jayant ^a  

^a GENERAL ELECTRIC COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84895223636     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1987.23240     Document Type: Article

References (10)

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2. R. W. Cohen, D. W. Tsand, and K. P. Lisiak, “High performance planar power MOSFET's,” IEEE Trans. Electron Devices, vol. ED-27, p. 340, 1980.
3. S. G. Sun and J. D. Plummer, “Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors,” IEEE Trans. Electron Devices, vol. ED-27, p. 356, 1980.
4. H.-R. Chang and B. J. Baliga, “Impact of cell breakdown upon power DMOSFET on-resistance,” presented at the 45th Device Research Conf., June 22–24, 1987.
5. Powertechnics Magazine, 14, Sept. 1986.
6. D. Ueda, H. Takagi, and G. Kano, “A new vertical power MOSFET structure with extremely reduced on-resistance,” IEEE Trans. Electron Devices, vol. ED-32, p. 2, 1985.
7. 2,” in IEDM Tech. Dig., p. 638, 1986.
8. S. Horiguchi, T. Kobayashi, M. Miyake, M. Oda, and K. Kiuchi, “Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm oxide,” in IEDM Tech. Dig., p. 761, 1985.
9. S. G. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, p. 1497, 1980.
10. S. J. Fonash, “Damage effects in dry etching,” Solid State Technol., vol. 28, no. 4, p. 201, 1985.