A LOW-OVERHEACDO HERENCSEO LUTION FOR MULTIPROCESSORS WITH PRIVATE CACHE MEMORIES

Proceedings - International Symposium on Computer Architecture

Volumn 1998-June, Issue , 1998, Pages 284-290

  Papamarcos, Mark S ^a   Patel, Janak H ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; MULTIPROCESSING SYSTEMS;

ANALYSIS METHOD; APPROXIMATE ANALYSIS; BUS TRAFFIC; CACHE COHERENCE; CACHE MODULES; MODULARS; PERFORMANCE; PROCESSOR UTILIZATION; SHARED BUS; WAIT TIME;

BUSES;

EID: 84894588328     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/285930.285987     Document Type: Conference Paper

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