Challenges in 3D memory manufacturing and process integration

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2013, Pages

  Chandrasekaran, Naga ^a  

^a MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84894361777     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2013.6724621     Document Type: Conference Paper

References (5)

1. G. Atwood, "Current and Emerging Memory Technology Landscape", 2011, Flash Summit 2011, CA
2. K. Prall, N. Ramaswamy, W. Kinney, K. Holtzclaw, X. Chen, J. Strand, and R. Bez, "An Update on Emerging Memory: Progress to 2Xnm", Memory Workshop (IMW), 2012 4th IEEE International, Milan, May 2012
3. N. Chandrasekaran, S. Hues, S. Lu, D. Li, C. Bishop, " Characterization and Metrology Challenges for Emerging Memory Technology Landscape", Frontiers of Characterization and Metrology for Nanoelectronics, NIST, Gaithesburg, p. 24, 2013
4. J. Beyersdorfer, F. Altmann, C. Grobe, S. Hubner, M. Simon-Najasek, A. Graff, "Preparation on 3D Interconnects", EFUG Meeting, 2011, Bordeaux
5. G. Fleeman, "3D and 2.5D Challenges", GSA/Sematech Memory Conference, Tokyo, Japan, Apr 2012