A high-efficiency back-bias generator with cross-coupled hybrid pumping circuit for sub-1.5 v DRAM applications

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 188-191

  Min, Kyeong Sik ^a   Jin, Kyo Won ^a   Kim, Ji Beom ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CROSS-COUPLED; HIGH-EFFICIENCY; LOW VOLTAGES; PUMPING CIRCUITS; PUMPING CURRENT; PUMPING EFFICIENCY;

EFFICIENCY; PUMPS;

COUPLED CIRCUITS;

EID: 84893797812     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. Nakagome et al., "A 1.5 V circuit technology for 64Mb DRAMs," in Symp. VLSI Cir. Dig. Tech. Papers, 1990, pp. 17-18.
2. A. Sekiyama et al., "A 1-V operating 256-kb full-CMOS SRAM," IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 776-782, May 1992.
3. D. Takashima et al., "Standby/active mode logic for sub-1-V operating ULSI memory," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 441-447, April 1994.
4. Y. Tsukikawa et al., "An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAM's," in Symp. VLSI Cir. Dig. Tech Papers, 1993, pp. 85-86.
5. T. B. Cho and P. R. Gray, "A 10-bit, 20 MS/s, 35 mW pipeline A/D converter," in IEEE Custom Integrated Circuit Conference, 1994, pp. 499-502.
6. P. Favrat et al., "A high-efficiency CMOS voltage doubler," in IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, March 1998.