False path elimination in quasi-static scheduling

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 964-970

  Arrigoni, G ^a   Duchini, L ^a   Lavagno, L ^b   Passerone, C ^b   Watanabe, Y ^c  

^a Loquendo SpA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONDITIONAL EXPRESSIONS; MEMORY REQUIREMENTS; QUASI-STATIC; QUASI-STATIC SCHEDULING; RUNNING TIME; SEMI-AUTOMATIC ALGORITHMS; SOFTWARE PARTITIONS; SYNCHRONIZATION CHANNELS;

AUTOMATION; DIGITAL STORAGE; EMBEDDED SYSTEMS; EXHIBITIONS; SCHEDULING; SPECIFICATIONS;

DESIGN;

EID: 84893779546     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998416     Document Type: Conference Paper

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