FreezeFrame: Compact test generation using a frozen clock strategy

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 747-752

  Santoso, Yanti ^a   Merten, Matthew ^a   Rudnick, Elizabeth M ^a   Abramovici, Miron ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT STATE; CLOCK TESTING; COMPACT TEST SEQUENCES; DYNAMIC COMPACTION METHOD; NEW APPROACHES; OVERALL COSTS; TEST APPLICATION TIME; TEST GENERATIONS;

EXHIBITIONS; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

CLOCKS;

EID: 84893610857     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761214     Document Type: Conference Paper

References (12)

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