Analysis and verification of board power delivery network impact on DDR3L memory interface in ARM SoC application

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2013

Volumn , Issue , 2013, Pages 215-218

  Tran, Dinh T ^a   Kim, Gawon ^a   Min, Max Sunghwan ^a   Bautista, Harold ^a   Zhou, Nian ^a   Choi, Baekkyu ^b   Cha, Seungyong ^c   You, Se Ho ^c  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

^c Samsung Electronics Corporation (SEC) Package Development Team Semiconductor R and D Center   (South Korea)

Author keywords

ARM SoC; board PDN; DDR3L

Indexed keywords

ELECTRIC POWER TRANSMISSION; ELECTRONICS PACKAGING; TIME DOMAIN ANALYSIS; TIMING JITTER;

ANALYSIS AND VERIFICATIONS; ARM SOC; BOARD PDN; DDR3L; FREQUENCY DOMAINS; POWER DELIVERY NETWORK; POWER DELIVERY NETWORK (PDN); SIMULATION AND MODELING;

COMPUTER SIMULATION;

EID: 84893574304     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2013.6703502     Document Type: Conference Paper

References (4)

1. Laddha, V. and Swaminathan, M., "Correlation of PDN impedance with jitter and voltage margin for high speed channels" in Proceedings of 2008 Electrical Performance of Electronic Packaging (EPEP), pp. 73-76.
2. Swaminathan, M. and Eugin, A. E., Power Integrity Modeling and Design for Semiconductors and Systems, Prentice hall, 2007.
3. Kyung Suk (Dan) Oh and Xing Chao (Chuck) Yuan, High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting, Prentice hall, 2011.
4. Hall, S. H. &Heck, H. L., Advanced Signal Integrity for High-Speed Digital Designs, IEEE: Wiley, 2008.