Retiming sequential circuits with multiple register classes

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 650-656

  Eckl, Klaus ^a   Legl, Christian ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL LOGIC; BASIC THEORY; CIRCUIT PERFORMANCE; CLOCK PERIOD MINIMIZATION; NEW APPROACHES; RETIMING; SYNCHRONOUS CIRCUITS;

CLOCKS; EXHIBITIONS;

DESIGN;

EID: 84893570873     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761198     Document Type: Conference Paper

References (19)

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