Challenges in spacer process development for leading-edge high-k metal gate technology

Physica Status Solidi (C) Current Topics in Solid State Physics

Volumn 11, Issue 1, 2014, Pages 73-76

  Koehler, Fabian ^a   Triyoso, Dina H ^a   Hussain, Itasham ^a   Antonioli, Bianca ^a   Hempel, Klaus ^a  

^a GLOBALFOUNDRIES   (Germany)

Author keywords

Atomic layer deposition; Gate encapsulation liners; High k metal gate technology; Silicon nitride spacers

Indexed keywords

DEVICE PERFORMANCE; GATE ENCAPSULATION; HIGH-K METAL GATES; LOW DEPOSITION TEMPERATURE; LOW-POWER CONSUMPTION; MILLER CAPACITANCE; PROCESS DEVELOPMENT; TRANSISTOR PERFORMANCE;

DEPOSITION; FILM GROWTH; GATE DIELECTRICS; HAFNIUM OXIDES; METALS; SILICON NITRIDE; TRANSISTORS;

ATOMIC LAYER DEPOSITION;

EID: 84892884682     PISSN: 18626351     EISSN: 16101642     Source Type: Journal    
DOI: 10.1002/pssc.201300157     Document Type: Article

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