Writing Testbenches using Systemverilog

Writing Testbenches using SystemVerilog

Volumn , Issue , 2006, Pages 1-411

  Bergeron, Janick ^a  

^a SYNOPSYS INC   (United States)

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EID: 84892320497     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/0-387-31275-7     Document Type: Book

References (48)

1. Cohen, Venkataramanan and Kumari, "SystemVerilog Assertion Handbook", VhdlCohen Publishing, 2005
2. Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale, "Verification Methodology Manual for SystemVerilog", Springer 2005, ISBN 0-387-25538-9
3. Before anyone paints me as a Verilog bigot, I wish to inform my readers that I learned VHDL first and have always had a slight preference toward VHDL over Verilog.
4. If you know of a verification-related resource or an error in this book that is not mentioned in the Web site, please let me know via email at janick@bergeron. com. I thank you in advance.
5. To my wife's chagrin who likes shaking any box bearing her name.
6. See Appendix A for a set of coding guidelines.
7. And it is. By a long shot.
8. But not necessarily achievable. For example, the default clause in a fully specified case statement should never be executed.
9. C++ still lacks a native concept of time, concurrency and instantiation.
10. Harry Foster and Lionel Bening, "Principles of Verifiable RTL Design", second edition, Kluwer Academic Publisher, ISBN 0-7923-7368-5.
11. See http://www.eda.org/ovl.
12. The formal verification community calls these input assertions "constraints." I used the term "assumptions" to differentiate them from randomgeneration constraints, which are randomization concepts.
13. However, many financial and sports pundits make a good living predicting an essentially random process. With enough pundits, you can always find one that has made the correct "prediction".
14. Faisal Haque, Jon Michelson and Khizar Khan, "The Art of Verification with VERA", http://www.verificationcentral.com
15. As specified in the architecture specification document, not in the implementation.
16. It is used to produce consonant sounds, such as the sh sound. It is then mixed with a shaped base frequency used to produce vowel sounds, such as the a sound, which hopefully creates intelligible speech.
17. You want to verify that, when the datapath is put into normal operation mode, the multiplexer is functionally correct and the input value is indeed coming from the random number generator.
18. See "IEEE P1364.1 Standard for Verilog Register Transfer Level Synthesis" prepared by the Verilog Synthesis Interoperability Working Group of the Design Automation Standards Committee.
19. Do not think, "It won't be my problem." You may very well be that person and you may not be able to understand your own code weeks later.
20. 93% cheaper in the 3 years since the first edition of this book!
21. That, however, is pretty much the same⋯
22. There are restrictions on the types that can be used within a packed struct. See the SystemVerilog LRM for more details.
23. A reference is similar to a pointer.
24. Inheritance will be discussed in more detail in "Inheritance" on page 153.
25. Why not make this derived class always a bad frame? Because generating a stream containing a mix of good and bad frames would require instantiating a mix of different classes. This way, only one class needs to be instantiated. The class will decide on its own whether the frame is good. And this approach is easier to constrain.
26. Simulators would be free to execute initial blocks first.
27. That is not strictly true but that is what happens in practice.
28. Some timing control statements can be inactive if the condition they are supposed to wait for is already true.
29. The execution of class methods as module or program threads is not clearly defined in the SystemVerilog standard and is being clarified by the P1800 Working Group. Verify with your simulator which exact interpretation is being used.
30. I borrowed this term from VHDL. SystemVerilog does not explicitly defines a term for zero-delay cycles.
31. Because wires are driven, not assigned. The value from each parallel construct would contribute to the final logic value on the wire, without overwriting the other.
32. You should avoid depending on this behavior.
33. Computer scientists have a very narrow definition of a semaphore that is probably not met by this implementation. However, it is good enough for now.
34. This specific execution order is only an example. The initial blocks could execute in reverse order with equally catastrophic results.
35. The task hw-reset contains delay control statements. The task should contain a semaphore to detect concurrent activation. You can read more about this issue in "Non-Re-Entrant Tasks" on page 188.
36. SystemVerilog has a standard waveform database called the VCD file. Although all waveform viewers can display simulation results from a VCD file, all of the more advanced viewers use their own proprietary database to store additional signal information.
37. The logic value on input d0 is ignored and a 1 is always loaded.
38. They all include timing control statements. They should have a semaphore to detect concurrent activation. See "Non-Re-Entrant Tasks" on page 188.
39. Exponential growth follows a Kn curve. Factorial growth follows a n! curve, where n! = 1 x 2 x 3 x 4 x⋯ x (n-2) x (n-1) x n.
40. The entire bus-functional model should be protected using a semaphore to prevent concurrent access to the interface signals. See "From Bus-Functional Tasks to Bus-Functional Model" on page 236.
41. Make sure the task is declared as automatic or these concurrent invocations will clobber each other! See section titled "Non-Re-Entrant Tasks" on page 188.
42. In fact, one was cut and pasted from the other!
43. Because methods are usually invoked without arguments and usually make use of random variables in the class being randomized, the solver would not know which variables to solve before calling the method. Thus the method may be called with unsolved-for variable values.
44. But if it is relevant, then it should be modeled.
45. Actually, since the latter is easier to design, its latency is made to match that of the input formatter, whatever it may be.
46. Unless of course a specific latency is required, in which case it should be specified in the specification document. And if something is specified, it should be modeled and verified.
47. An error in my opinion. See the next section titled "The Benefits of Transaction-Level Models".
48. Unless the intellectual property is in the function itself, such as a DSP algorithm.