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Volumn , Issue , 2005, Pages 1-179

Taxonomies for the development and verification of digital systems

Author keywords

[No Author keywords available]

Indexed keywords


EID: 84892220246     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/b104217     Document Type: Book
Times cited : (21)

References (60)
  • 1
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    • Anderson, T.1    Bhagat, R.2
  • 2
    • 84892204681 scopus 로고    scopus 로고
    • Verification reuse enables design reuse
    • December 23
    • [AND 02] Tom Anderson, "Verification reuse enables design reuse", Electronic Engineering Times, December 23, 2002.
    • (2002) Electronic Engineering Times
    • Anderson, T.1
  • 3
    • 84892363308 scopus 로고    scopus 로고
    • Functional verification in the context of design reuse
    • January
    • [AND 04] Thomas L. Anderson, "Functional Verification in the Context of Design Reuse", DesignCon 2004 Conference Proceedings, January, 2004.
    • (2004) DesignCon 2004 Conference Proceedings
    • Anderson, T.L.1
  • 17
    • 16244396766 scopus 로고    scopus 로고
    • Transaction level modeling: Flows and use models
    • [DON 04] Adam Donlin, "Transaction level modeling: flows and use models", Proceedings of CODES+ISSS 2004, pp. 75-80, 2004.
    • (2004) Proceedings of CODES+ISSS 2004 , pp. 75-80
    • Donlin, A.1
  • 18
    • 84947924601 scopus 로고    scopus 로고
    • SystemC for the design and modeling of programmable systems
    • [DONBR 04] Adam Donlin, Axel Braun, and Adam Rose, "SystemC for the Design and Modeling of Programmable Systems", Proceedings of FPL 2004, pp. 811-820, 2004
    • (2004) Proceedings of FPL 2004 , pp. 811-820
    • Donlin, A.1    Braun, A.2    Rose, A.3
  • 19
    • 0026963771 scopus 로고
    • The Design Cube-A Model for VHDL Design flow Representation
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  • 21
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    • Rapid prototyping of digital systems with COTS/ASIC components
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    • Famorzadeh, S.1
  • 35
    • 84892353298 scopus 로고
    • System-level synthesis and simulation VHDL: A taxonomy and proposal towards standardization
    • [MADI 95] V. Madisetti, "System-Level Synthesis and Simulation VHDL: A Taxonomy and Proposal Towards Standardization", VIUF Spring, 1995 Proceedings, 1995.
    • (1995) VIUF Spring, 1995 Proceedings
    • Madisetti, V.1
  • 39
    • 84892212828 scopus 로고    scopus 로고
    • Accellera, June, 2003
    • [OVL] OVL Reference Manual, Accellera, http://www.verificationlib.org, June, 2003.
    • OVL Reference Manual
  • 41
    • 84892219599 scopus 로고    scopus 로고
    • RASSP Taxonomy Working Group RTWG, February 23
    • [RASSP 98] VHDL Modeling Terminology and Taxonomy Revision 2.4, RASSP Taxonomy Working Group (RTWG), http://www.eda.org/rassp/index.html, February 23, 1998.
    • (1998) VHDL Modeling Terminology and Taxonomy Revision 2.4
  • 42
    • 0033295559 scopus 로고    scopus 로고
    • System design-traditional concepts and new paradigms
    • October
    • [SAN 99] A. Sangiovanni-Vincentelli and A. Ferrari, "System Design-Traditional Concepts and New Paradigms", ICCD 99, pp. 2-12, October, 1999.
    • (1999) ICCD 99 , pp. 2-12
    • Sangiovanni-Vincentelli, A.1    Ferrari, A.2
  • 43
    • 0035509391 scopus 로고    scopus 로고
    • Platform-based design and software design methodology for embedded systems
    • November-December
    • [SAN 01] Alberto Sangiovanni-Vincentelli and Grant Martin, "Platform-Based Design and Software Design Methodology for Embedded Systems", IEEE Design & Test of Computers, pp. 23-33, November-December, 2001.
    • (2001) IEEE Design & Test of Computers , pp. 23-33
    • Sangiovanni-Vincentelli, A.1    Martin, G.2
  • 44
    • 0013200744 scopus 로고    scopus 로고
    • Defining platform-based design
    • February 5
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.