Scalable hardware verification with symbolic simulation

Scalable Hardware Verification with Symbolic Simulation

Volumn , Issue , 2006, Pages 1-178

  Bertacco, Valeria ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84892206931     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/0-387-29906-8     Document Type: Book

References (209)

1. Valeria Bertacco and Maurizio Damiani. Boolean function representation based on disjoint-support decompositions. In ICCD, Proceedings of the International Conference on Computer Design, pages 27-33, October 1996.
2. Valeria Bertacco and Maurizio Damiani. The disjunctive decomposition of logic functions. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 78-82, November 1997.
3. Valeria Bertacco. Achieving Scalable Hardware Verification with Symbolic Simulation. PhD thesis, Stanford University, 2003.
4. Karl Brace, Richard Rudell, and Randal E. Bryant. Efficient implementation of a BDD package. In DAC, Proceedings of Design Automation Conference, pages 40-45, 1990.
5. Stephen Plaza and Valeria Bertacco. Boolean operations on decomposed functions. In International Workshop on Logic Synthesis, pages 310-317, June 2005.
6. Stephen Plaza and Valeria Bertacco. STACCATO: Disjoint support decompositions from BDDs through symbolic kernels. In ASPDAC, Proceedings of the Asia South Pacific Design Automation Conference, pages 276-279, January 2005.
7. Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, and Gil Shurek. Test program generation for functional verification of PowerPC processors in IBM. In DAC, Proceedings of Design Automation Conference, pages 279-285, June 1995.
8. Mark D. Aagaard, Robert B. Jones, and Carl-Johan H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, Proceedings of Design Automation Conference, pages 402-407, June 1999.
9. Robert L. Ashenhurst. The decomposition of switching functions. In Proceedings of the International Symposium on the Theory of Switching, Part I 29, pages 74-116, 1957.
10. Randal E. Bryant, Derek Beatty, Karl Brace, Kyeongsoon Cho, and Thomas Sheffler. COSMOS: A compiled simulator for MOS circuits. In DAC, Proceedings of Design Automation Conference, pages 9-16, June 1987.
11. Franc Brglez, David Bryan, and Krzysztof Kozmiriski. Combinational profiles of sequential benchmark circuits. In ISCAS, Proceedings of the International Symposyium on Circuits and Systems, pages 1929-1934, May 1989.
12. Derek L. Beatty, Randall E. Bryant, and Carl-Johann H. Seger. Synchronous circuit verification by symbolic simulation: An illustration. In Proceedings of Sixth MIT Conference on Advanced Research in VLSI, pages 98-112, 1990.
13. Randal E. Bryant and Yirng-An Chen. Verification of arithmetic circuits using binary moment diagrams. International Journal on Software Tools for Technology Transfer, 3(2):137-155, 2001.
14. Jerry R. Burch, Edward M. Clarke, David E. Long, Ken L. McMillan, and David L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(4):401-424, 1994.
15. Zeev Barzilai, J. LawrenceCarter, Barry K. Rosen, and Joseph D. Rutledge. HSS - a high-speed simulator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 601-617, July 1987.
16. Valeria Bertacco and Maurizio Damiani. Boolean function representation based on disjoint-support decompositions. In ICCD, Proceedings of the International Conference on Computer Design, pages 27-33, October 1996.
17. Valeria Bertacco and Maurizio Damiani. Boolean function representation using parallel-access diagrams. In Proceedings of the Sixth Great Lakes Symposium on VLSI, March 1996.
18. Valeria Bertacco and Maurizio Damiani. The disjunctive decomposition of logic functions. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 78-82, November 1997.
19. Valeria Bertacco, Maurizio Damiani, and Stefano Quer. Cycle-based symbolic simulation of gate-level synchronous circuits. In DAC, Proceedings of Design Automation Conference, pages 391-396, June 1999.
20. Janick Bergeron. Writing Testbenches: Functional Verification of HDL Models. Kluwer Academic Publishers, 2nd edition, 2003.
21. Valeria Bertacco. Achieving Scalable Hardware Verification with Symbolic Simulation. PhD thesis, Stanford University, 2003.
22. Soumitra Bose and Allan Fisher. Verifying pipelined hardware using symbolic logic simulation. In ICCD, Proceedings of the International Conference on Computer Design, pages 217-221, October 1989.
23. Jerry R. Burch and David E. Long. Efficient Boolean function matching. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 408-411, November 1992.
24. Beate Bollig, Martin Lobbing, and Ingo Wegener. Simulated annealing to improve variable orderings for OBDDs. In International Workshop on Logic Synthesis, pages 5.1-5.10, May 1995.
25. Robert K. Brayton and Curt McMullen. The decomposition and factorization of Boolean expressions. In ISCAS, Proceedings of the International Symposyium on Circuits and Systems, pages 49-54, 1982.
26. Valeria Bertacco and Kunle Olukotun. Efficient state representation for symbolic simulation. In DAC, Proceedings of Design Automation Conference, June 2002.
27. Karl Brace, Richard Rudell, and Randal E. Bryant. Efficient implementation of a BDD package. In DAC, Proceedings of Design Automation Conference, pages 40-45, 1990.
28. Robert K. Brayton, Richard Rudell, Alberto Sangiovanni-Vincentelli, and Albert R. Wang. MIS: A multiple-level logic optimization system. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 6(6):1062-1081, November 1987.
29. Randall E. Bryant. Symbolic verification of MOS circuits. In Proceedings of 1985 Chapel Hill Conference on VLSI, pages 419-438, May 1985.
30. Randal E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computers, 35(8):677-691, August 1986.
31. Randal E. Bryant. Symbolic Boolean manipulation with ordered binarydecision diagrams. ACM Computing Surveys, 24(3):293-318, September 1992.
32. Olivier Coudert, Christian Berthet, and Jean Christophe Madre. Verification of synchronous sequential machines based on symbolic execution. In Automatic Verification Methods for Finite State Systems, International Workshop, volume 407 of Lecture Notes in Computer Science, pages 365-3. Springer, June 1989.
33. Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, and Stefano Quer. Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits. In DAC, Proceedings of Design Automation Conference, pages 728-733, June 1997.
34. Gianpiero Cabodi, Paolo Camurati, and Stefano Quer. Improved reachability analysis of large finite state machine. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 354-360, November 1996.
35. A. Chandra, V. Iyengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal. AVPGEN - a test generator for architecture verification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(2):188-200, June 1995.
36. William C. Carter, William H. Joyner, and Daniel Brand. Symbolic simulation for correct machine design. In DAC, Proceedings of Design Automation Conference, pages 280-286, June 1979.
37. Olivier Coudert and Jean Christophe Madre. A unified framework for the formal verification of sequential circuits. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 126-129, November 1990.
38. Olivier Coudert and Jean Christophe Madre. Implicit and incremental computation of primes and essential primes of Boolean functions. In DAC, Proceedings of Design Automation Conference, pages 36-39, June 1992.
39. Srihari Cadambi, Chandra S. Mulpuri, and Pranav N. Ashar. A fast, inexpensive and scalable hardware acceleration technique for functional simulation. In DAC, Proceedings of Design Automation Conference, pages 570-575, June 2002.
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43. Masahiro Fujita, Hisanori Fujisawa, and Nobuaki Kawato. Evaluation and improvements of Boolean comparison method based on binary decision diagrams. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 2-5, November 1988.
44. Masahiro Fujita, Patrick McGeer, and Jerry Yang. Multi-terminal binary decision diagrams: An efficient datastructure for matrix representation. Formal Methods in System Design, 10(2-3):149-169, 1997.
45. Amit Goel and Randal E. Bryant. Set manipulation with Boolean functional vectors for symbolic reachability analysis. In DATE, Design, Automation and Test in Europe Conference, pages 10816-10821, March 2003.
46. Craig Hansen. Hardware logic simulation by compilation. In DAC, Proceedings of Design Automation Conference, pages 712-716, June 1988.
47. Scott Hauck. Multi-FPGA Systems. PhD thesis, University of Washington, Dept. of Computer Science and Engineering, 1995.
48. Alan J. Hu and David L. Dill. Reducing BDD size by exploiting functional dependencies. In DAC, Proceedings of Design Automation Conference, pages 266-271, June 1993.
49. Faisal I. Haque, Khizar A. Khan, and Jonathan Michelson. The Art of Verification with Vera. Verification Central, 2001.
50. Yoav Hollander, Matthew Morley, and Amos Noy. The e language: A fresh separation of concerns. In Technology of Object-Oriented Languages and Systems, volume TOOLS-38, pages 41-50, March 2001.
51. Pei-Hsin Ho, Thomas Shiple, Kevin Harer, James Kukula, Robert Damiano, Valeria Bertacco, Jerry Taylor, and Jiang Long. Smart simulation using collaborative formal and simulation engines. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 120-126, November 2000.
52. Gerard Huet. Higher order unification 30 years later. In Theorem Proving in Higher Order Logics, volume 2410 of Lecture Notes in Computer Science, pages 3-12. Springer-Verlag, August 2002.
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55. Prabhat Jain and Ganesh Gopalakrishnan. Efficient symbolic simulationbased verification using the parametric form of Boolean expressions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13:1005-1015, August 1994.
56. Steven Johnson. View from the fringe of the fringe. In CHARME, volume 2144 of Lecture Notes in Computer Science, pages 1-12. Springer-Verlag, September 2001.
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63. James C. King. Symbolic execution and program testing. Communications of the ACM, 19(7):385-394, July 1976.
64. Alferd Kolbl, James Kukula, and Robert Damiano. Symbolic RTL simulation. In DAC, Proceedings of Design Automation Conference, pages 47-52, June 2001.
65. Michael Kantrowitz and Lisa M. Noack. I'm done simulating; now what? verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor. In DAC, Proceedings of Design Automation Conference, pages 325-330, June 1996.
66. Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Marc Edwards, and Yaron Kashai. A framework for object oriented hardware specification, verification and synthesis. In DAC, Proceedings of Design Automation Conference, pages 413-418, June 2001.
67. Oded Lachish, Eitan Marcus, Shmuel Ur, and Avi Ziv. Hole analysis for functional coverage data. In DAC, Proceedings of Design Automation Conference, pages 807-812, June 2002.
68. Frederic Mailhot and Giovanni De Micheli. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12:599-620, May 1993.
69. S.-I. Minato. Zero-suppressed bdds for set manipulation in combinatorial problems. In DAC, Proceedings of Design Automation Conference, pages 272-277, June 1993.
70. In-Ho Moon, Hee Hwan Kwak, James Kukula, Thomas Shiple, and Carl Pixley. Simplifying circuits for formal verification using parametric representation. In FMCAD, Proceedings of International Conference on Formal Methods in Computer-Aided Design, pages 52-69. Springer-Verlag, 2002.
71. In-Ho Moon, James Kukula, Kavita Ravi, and Fabio Somenzi. To split or to conjoin: The question in image computation. In DAC, Proceedings of Design Automation Conference, pages 23-28, June 2000.
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73. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. ESPRESSO-SIGNATURE: A new exact minimizer for logic functions. In DAC, Proceedings of Design Automation Conference, pages 618-624, June 1993.
74. Sharad Malik, Albert Wang, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 6-9, November 1988.
75. Stephen Plaza and Valeria Bertacco. Boolean operations on decomposed functions. In International Workshop on Logic Synthesis, pages 310-317, June 2005.
76. Stephen Plaza and Valeria Bertacco. STACCATO: Disjoint support decompositions from BDDs through symbolic kernels. In ASPDAC, Proceedings of the Asia South Pacific Design Automation Conference, pages 276-279, January 2005.
77. Gregory F. Pfister. The yorktown simulation engine: Introduction. In DAC, Proceedings of Design Automation Conference, pages 51-54, January 1982.
78. Gerd Ritter, Hans Eveking, and Holger Hinrichsen. Formal verification of designs with complex control by symbolic simulation. In CHARME, Proceedings of Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pages 234-249. Springer-Verlag, 1999.
79. Kavita Ravi and Fabio Somenzi. High density reachability analysis. In IC-CAD, Proceedings of the International Conference on Computer Aided Design, pages 154-158, November 1995.
80. Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 42-47, November 1993.
81. Tsutomu Sasao. Totally undecomposable functions: Applications to efficient multiple-valued decompositions. In ISMVL, pages 59-65, 1999.
82. Carl-Johan H. Seger and Randal E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2):147-189, 1995.
83. Claude E. Shannon. The synthesis of two-terminal switching circuits. Bell Systems Technical Journal, 28(1):59-98, 1949.
84. Theodore Singer. The decomposition chart as a theoretical aid. Technical Report BL-4, Sec. III, Harvard Computational Laboratory, 1953.
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87. Herve Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDDs. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 130-133, November 1990.
88. Miroslav N. Velev, Randal E. Bryant, and Alok Jain. Efficient modeling of memory arrays in symbolic simulation. In CAV, Proceedings of International Conference on Computer Aided Verification, volume 1254 of Lecture Notes in Computer Science, pages 388-399. Springer-Verlag, June 1997.
89. C. A. J. Van Eijk and Jochen A. G. Jess. Exploiting functional dependencies in finite state machine verification. In ED&TC, Proceedings of the European Design and Test Conference, pages 9-14, March 1996.
90. Dong Wang, Edmund Clarke, Yunshan Zhu, and Jim Kukula. Using cutwidth to improve symbolic simulation and Boolean satisfiability. In HLDVT, IEEE International High Level Design Validation and Test Workshop, pages 165-170, November 2001.
91. Chris Wilson and David L. Dill. Reliable verification using symbolic simulation with scalar values. In DAC, Proceedings of Design Automation Conference, pages 124-129, June 2000.
92. Chris Wilson, David L. Dill, and Randal E. Bryant. Symbolic simulation with approximate values. In FMCAD, Proceedings of International Conference on Formal Methods in Computer-Aided Design, volume 1954 of Lecture Notes in Computer Science, pages 470-485. Springer, November 2000.
93. Laung-Terng Wang, Nathan E. Hoover, Edwin H. Porter, and John J. Zasio. SSIM: A software levelized compiled-code simulator. In DAC, Proceedings of Design Automation Conference, pages 2-8, June 1987.
94. James Christofer Wilson. Symbolic Simulation Using Automatic Abstraction of Internal Node Values. PhD thesis, Stanford University, December 2001.
95. Saeyang Yang. Logic synthesis and optimization benchmarks user guide, version 3.0. Technical report, Microelectronics Center of North Carolina, January 1991.
96. Jin Yang and Carl-Johan H. Seger. Introduction to generalized symbolic trajectory evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3):345-353, 2003.
97. Jun. Yuan, Kurt Schultz, Carl Pixley, Hiller Miller, and Adnan Aziz. Modeling design constraints and biasing using bdds in simulation. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 584-590, November 1999.
98. Aharon Aharon, Dave Goodman, Moshe Levinger, Yossi Lichtenstein, Yossi Malka, Charlotte Metzger, Moshe Molcho, and Gil Shurek. Test program generation for functional verification of PowerPC processors in IBM. In DAC, Proceedings of Design Automation Conference, pages 279-285, June 1995.
99. Randal E. Bryant and Yirng-An Chen. Verification of arithmetic circuits using binary moment diagrams. International Journal on Software Tools for Technology Transfer, 3(2):137-155, 2001.
100. Jerry R. Burch, Edward M. Clarke, David E. Long, Ken L. McMillan, and David L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(4):401-424, 1994.
101. Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, and Joseph D. Rutledge. HSS - a high-speed simulator. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 601-617, July 1987.
102. Janick Bergeron. Writing Testbenches: Functional Verification of HDL Models. Kluwer Academic Publishers, 2nd edition, 2003.
103. Jerry R. Burch and David E. Long. Efficient Boolean function matching. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 408-411, November 1992.
104. Beate Bollig, Martin Lobbing, and Ingo Wegener. Simulated annealing to improve variable orderings for OBDDs. In International Workshop on Logic Synthesis, pages 5.1-5.10, May 1995.
105. Karl Brace, Richard Rudell, and Randal E. Bryant. Efficient implementation of a BDD package. In DAC, Proceedings of Design Automation Conference, pages 40-45, 1990.
106. Randal E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computers, 35(8):677-691, August 1986.
107. Randal E. Bryant. Symbolic Boolean manipulation with ordered binarydecision diagrams. ACM Computing Surveys, 24(3):293-318, September 1992.
108. Olivier Coudert, Christian Berthet, and Jean Christophe Madre. Verification of synchronous sequential machines based on symbolic execution. In Automatic Verification Methods for Finite State Systems, International Workshop, volume 407 of Lecture Notes in Computer Science, pages 365-3. Springer, June 1989.
109. A. Chandra, V. Iyengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, J. Yoon, R. Armoni, D. Geist, and Y. Wolfsthal. AVPGEN - a test generator for architecture verification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(2):188-200, June 1995.
110. Srihari Cadambi, Chandra S. Mulpuri, and Pranav N. Ashar. A fast, inexpensive and scalable hardware acceleration technique for functional simulation. In DAC, Proceedings of Design Automation Conference, pages 570-575, June 2002.
111. Charles J. De Vane. Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 154-161, November 1997.
112. Masahiro Fujita, Hisanori Fujisawa, and Nobuaki Kawato. Evaluation and improvements of Boolean comparison method based on binary decision diagrams. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 2-5, November 1988.
113. Masahiro Fujita, Patrick McGeer, and Jerry Yang. Multi-terminal binary decision diagrams: An efficient datastructure for matrix representation. Formal Methods in System Design, 10(2-3):149-169, 1997.
114. Craig Hansen. Hardware logic simulation by compilation. In DAC, Proceedings of Design Automation Conference, pages 712-716, June 1988.
115. Scott Hauck. Multi-FPGA Systems. PhD thesis, University of Washington, Dept. of Computer Science and Engineering, 1995.
116. Faisal I. Haque, Khizar A. Khan, and Jonathan Michelson. The Art of Verification with Vera. Verification Central, 2001.
117. Yoav Hollander, Matthew Morley, and Amos Noy. The e language: A fresh separation of concerns. In Technology of Object-Oriented Languages and Systems, volume TOOLS-38, pages 41-50, March 2001.
118. Gerard Huet. Higher order unification 30 years later. In Theorem Proving in Higher Order Logics, volume 2410 of Lecture Notes in Computer Science, pages 3-12. Springer-Verlag, August 2002.
119. Steven Johnson. View from the fringe of the fringe. In CHARME, volume 2144 of Lecture Notes in Computer Science, pages 1-12. Springer-Verlag, September 2001.
120. Michael Kantrowitz and Lisa M. Noack. I'm done simulating; now what? verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor. In DAC, Proceedings of Design Automation Conference, pages 325-330, June 1996.
121. Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Marc Edwards, and Yaron Kashai. A framework for object oriented hardware specification, verification and synthesis. In DAC, Proceedings of Design Automation Conference, pages 413-418, June 2001.
122. Oded Lachish, Eitan Marcus, Shmuel Ur, and Avi Ziv. Hole analysis for functional coverage data. In DAC, Proceedings of Design Automation Conference, pages 807-812, June 2002.
123. Frédéric Mailhot and Giovanni De Micheli. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12:599-620, May 1993.
124. S.-I. Minato. Zero-suppressed bdds for set manipulation in combinatorial problems. In DAC, Proceedings of Design Automation Conference, pages 272-277, June 1993.
125. Sharad Malik, Albert Wang, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 6-9, November 1988.
126. Gregory F. Pfister. The yorktown simulation engine: Introduction. In DAC, Proceedings of Design Automation Conference, pages 51-54, January 1982.
127. Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 42-47, November 1993.
128. Herve Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. Implicit state enumeration of finite state machines using BDDs. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 130-133, November 1990.
129. Laung-Terng Wang, Nathan E. Hoover, Edwin H. Porter, and John J. Zasio. SSIM: A software levelized compiled-code simulator. In DAC, Proceedings of Design Automation Conference, pages 2-8, June 1987.
130. Jun. Yuan, Kurt Schultz, Carl Pixley, Hiller Miller, and Adnan Aziz. Modeling design constraints and biasing using bdds in simulation. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 584-590, November 1999.
131. Mark D. Aagaard, Robert B. Jones, and Carl-Johan H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, Proceedings of Design Automation Conference, pages 402-407, June 1999.
132. Randal E. Bryant, Derek Beatty, Karl Brace, Kyeongsoon Cho, and Thomas Sheffler. COSMOS: A compiled simulator for MOS circuits. In DAC, Proceedings of Design Automation Conference, pages 9-16, June 1987.
133. Derek L. Beatty, Randall E. Bryant, and Carl-Johann H. Seger. Synchronous circuit verification by symbolic simulation: An illustration. In Proceedings of Sixth MIT Conference on Advanced Research in VLSI, pages 98-112, 1990.
134. Valeria Bertacco, Maurizio Damiani, and Stefano Quer. Cycle-based symbolic simulation of gate-level synchronous circuits. In DAC, Proceedings of Design Automation Conference, pages 391-396, June 1999.
135. Soumitra Bose and Allan Fisher. Verifying pipelined hardware using symbolic logic simulation. In ICCD, Proceedings of the International Conference on Computer Design, pages 217-221, October 1989.
136. Valeria Bertacco and Kunle Olukotun. Efficient state representation for symbolic simulation. In DAC, Proceedings of Design Automation Conference, June 2002.
137. Randall E. Bryant. Symbolic verification of MOS circuits. In Proceedings of 1985 Chapel Hill Conference on VLSI, pages 419-438, May 1985.
138. Olivier Coudert, Christian Berthet, and Jean Christophe Madre. Verification of synchronous sequential machines based on symbolic execution. In Automatic Verification Methods for Finite State Systems, International Workshop, volume 407 of Lecture Notes in Computer Science, pages 365-3. Springer, June 1989.
139. Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, and Stefano Quer. Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits. In DAC, Proceedings of Design Automation Conference, pages 728-733, June 1997.
140. Gianpiero Cabodi, Paolo Camurati, and Stefano Quer. Improved reachability analysis of large finite state machine. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 354-360, November 1996.
141. William C. Carter, William H. Joyner, and Daniel Brand. Symbolic simulation for correct machine design. In DAC, Proceedings of Design Automation Conference, pages 280-286, June 1979.
142. Amit Goel and Randal E. Bryant. Set manipulation with Boolean functional vectors for symbolic reachability analysis. In DATE, Design, Automation and Test in Europe Conference, pages 10816-10821, March 2003.
143. Pei-Hsin Ho, Thomas Shiple, Kevin Harer, James Kukula, Robert Damiano, Valeria Bertacco, Jerry Taylor, and Jiang Long. Smart simulation using collaborative formal and simulation engines. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 120-126, November 2000.
144. James C. King. Symbolic execution and program testing. Communications of the ACM, 19(7):385-394, July 1976.
145. Alferd Kolbl, James Kukula, and Robert Damiano. Symbolic RTL simulation. In DAC, Proceedings of Design Automation Conference, pages 47-52, June 2001.
146. In-Ho Moon, James Kukula, Kavita Ravi, and Fabio Somenzi. To split or to conjoin: The question in image computation. In DAC, Proceedings of Design Automation Conference, pages 23-28, June 2000.
147. Gerd Ritter, Hans Eveking, and Holger Hinrichsen. Formal verification of designs with complex control by symbolic simulation. In CHARME, Proceedings of Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pages 234-249. Springer-Verlag, 1999.
148. Kavita Ravi and Fabio Somenzi. High density reachability analysis. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 154-158, November 1995.
149. Carl-Johan H. Seger and Randal E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2):147-189, 1995.
150. Miroslav N. Velev, Randal E. Bryant, and Alok Jain. Efficient modeling of memory arrays in symbolic simulation. In CAV, Proceedings of International Conference on Computer Aided Verification, volume 1254 of Lecture Notes in Computer Science, pages 388-399. Springer-Verlag, June 1997.
151. Dong Wang, Edmund Clarke, Yunshan Zhu, and Jim Kukula. Using cutwidth to improve'symbolic simulation and Boolean satisfiability. In HLDVT, IEEE International High Level Design Validation and Test Workshop, pages 165-170, November 2001.
152. Chris Wilson and David L. Dill. Reliable verification using symbolic simulation with scalar values. In DAC, Proceedings of Design Automation Conference, pages 124-129, June 2000.
153. Jin Yang and Carl-Johan H. Seger. Introduction to generalized symbolic trajectory evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3):345-353, 2003.
154. Mark D. Aagaard, Robert B. Jones, and Carl-Johan H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, Proceedings of Design Automation Conference, pages 402-407, June 1999.
155. Robert L. Ashenhurst. The decomposition of switching functions. In Proceedings of the International Symposium on the Theory of Switching, Part I 29, pages 74-116, 1957.
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