Evaluation of leakage reduction alternatives for deep submicron dynamic nonuniform cache architecture caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 22, Issue 1, 2014, Pages 185-190

  Bardine, Alessandro ^a   Comparetti, Manuel ^a,b   Foglia, Pierfrancesco ^a   Prete, Cosimo Antonio ^a  

^a UNIVERSITY OF PISA   (Italy)

^b RMC Srl   (Italy)

Author keywords

Leakage reduction techniques; nonuniform cache architecture (NUCA) cache; power consumption; wire delay

Indexed keywords

LEAKAGE POWER CONSUMPTION; LEAKAGE REDUCTION TECHNIQUES; MIGRATION MECHANISMS; NON-UNIFORM CACHE ARCHITECTURE; NON-UNIFORM CACHE ARCHITECTURES; PROCESS VARIATION; STATIC RANDOM ACCESS MEMORY; WIRE DELAYS;

CACHE MEMORY; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION;

WIRE;

EID: 84891793521     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2012.2231949     Document Type: Article

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