Memory-saving analysis of Petri nets

Design of Embedded Control Systems

Volumn , Issue , 2005, Pages 63-72

  Karatkevich, Andrei ^a  

^a UNIVERSITY OF ZIELONA GÓRA   (Poland)

Author keywords

analysis; formal models; Petri nets; simulation

Indexed keywords

EID: 84891419589     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/0-387-28327-7_6     Document Type: Chapter

References (18)

1. T. Murata, Petri nets: Properties, analysis and applications. Proceedings of the IEEE, 77(4), 548-580, (April 1989).
2. M. Heiner, Petri net-based system analysis without state explosion. High Performance Computing'98, Boston, pp. 1-10 (April 1998).
3. A. Valmari, The state explosion problem. In: W. Reisicg, G. Rozenberg (eds.), Lectures on Petri Nets I: Basic Models, LNCS Tutorials, LNCS 1491, Springer-Verlag pp. 429-528, (1998).
4. A. Valmari, State of the art report: Stubborn sets. Petri Nets Newsletter, 46, 6-14, (1994).
5. C. Girault, R. Valk Petri Nets for System Engineering: A Guide to Modeling, Verification, and Applications, Springer-Verlag (2003).
6. A. Karatkevich, M. Adamski, Deadlock analysis of Petri nets: Minimization of memory amount. In: Proceedings of 3rd ECS Conference, Bratislava, pp. 69-72 (2001).
7. A. G. Karatkevich, Dynamic reduction of Petri net reachability graphs. Radioelektronika i Informatika, 18(1), 76-82, Kharkov (2002) (in Russian).
8. A. Karatkevich, On algorithms for decyclisation of oriented graphs. In: DESDes'01. Przytok, Poland, pp. 35-40 (2001).
9. R. Janicki, M. Koutny, Optimal simulation, nets and reachability graphs. Technical Report No. 01-09, McMaster University, Hamilton (1991).
10. A. Karatkevich, Optimal simulation of a-nets. In: SRE-2000. Zielona Góra, pp. 205-210 (2000).
11. A. Lempel, Minimum feedback arc and vertex sets of a directed graph IEEE Transactions on Circuit Theory, CT-13(4), 399-403, (December 1966).
12. N. Deo, Graph Theory with Applications to Engineering and Computer Science. Prentice-Hall, New Jersey (1974).
13. B. Thelen, Investigation of Algorithms for Computer-Aided Logic Design of Digital Circuits. University of Karlsruhe (1988) (in German).
14. H.-J. Mathony, Universal logic design algorithm and its application to the synthesis of two-level switching circuits. In: Proceedings of the IEE, 136(3), 171-177, (1989).
15. J. Bieganowski, A. Karatkevich, Heuristics for Thelen's prime implicant method. In: MSK, Krakow, pp. 71-76 (November 2003) (in Polish).
16. A. Wẽgrzyn, A. Karatkevich, J. Bieganowski, Detection of deadlocks and traps in Petri nets by means of Thelen's prime implicant method, AMCS, 14(1), 113-121, (2004).
17. O. Coudert, J. K. Madre, New ideas for solving covering problems. In: Proceedings of the 32nd ACM/IEEE Conference on Design Automation, San Francisco, California, United States, pp. 641-646 (1995).
18. T. H. Cormen, Ch. E. Leiserson, R. L. Rivest, Introduction to Algorithms. MIT (1994).