Stealthy dopant-level hardware trojans

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 8086 LNCS, Issue , 2013, Pages 197-214

  Becker, Georg T ^a   Regazzoni, Francesco ^b,c   Paar, Christof ^a,d   Burleson, Wayne P ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c UNIVERSITY OF LUGANO   (Switzerland)

^d RUHR UNIVERSITY BOCHUM   (Germany)

Author keywords

Hardware trojans; Layout modifications; Malicious hardware; Trojan side channel

Indexed keywords

EMBEDDED SYSTEMS; INTEGRATED CIRCUIT DESIGN; MALWARE; MILITARY APPLICATIONS; SIDE CHANNEL ATTACK;

DOPANT LEVELS; INFRASTRUCTURE APPLICATIONS; LAYOUT MODIFICATION; MANUFACTURING PROCESS; OPTICAL INSPECTION; POST PROCESSING; SCIENTIFIC COMMUNITY; SIDE-CHANNEL;

HARDWARE SECURITY;

EID: 84890588314     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-40349-1_12     Document Type: Conference Paper

References (25)

1. Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., Sunar, B.: Trojan Detection using IC Fingerprinting. In: IEEE Symposium on Security and Privacy (SP 2007), pp. 296-310 (2007)
2. Brier, E., Clavier, C., Olivier, F.: Correlation Power Analysis with a Leakage Model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16-29. Springer, Heidelberg (2004)
3. Canright, D.: A very compact S-box for AES. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 441-455. Springer, Heidelberg (2005)
4. Defense Science Board. Report of the Defense Science Board Task Force on High Performance Microchip Supply. US DoD (February 2005)
5. Gierlichs, B., Batina, L., Tuyls, P., Preneel, B.: Mutual Information Analysis. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 426-442. Springer, Heidelberg (2008)
6. Gorman, C.: Counterfeit chips on the rise. IEEE Spectrum 49(6), 16-17 (2012)
7. Hamburg, M., Kocher, P., Marson, M.E.: Analysis of Intel's Ivy Bridge Digital Random Number Generator. Technical Report, Cryptography Research INC. (March 2012)
8. Hicks, M., Finnicum, M., King, S.T., Martin, M.M., Smith, J.M.: Overcoming an untrusted computing base: Detecting and removing malicious hardware automatically. In: IEEE Symposium on Security and Privacy (SP 2010), pp. 159-172 (2010)
9. Intel. Intel Digital Random Number Generator (DRNG) Software Implementation Guide, revision 1.1 (August 2012), http://software.intel.com/ sites/default/files/m/d/4/1/d/8/ 441IntelRDRNGSoftwareImplementationGuidefinalAug7.pdf
10. King, S.T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., Zhou, Y.: Designing and implementing malicious hardware. In: Proceedings of the 1st USENIX Workshop on Large-scale Exploits and Emergent Threats (LEET 2008), pp. 1-8 (2008)
11. Li, J., Lach, J.: At-speed delay characterization for IC authentication and Trojan horse detection. In: IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2008), pp. 8-14 (2008)
12. Lin, L., Kasper, M., Güneysu, T., Paar, C., Burleson, W.: Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 382-395. Springer, Heidelberg (2009)
13. Markoff, S.: Cyberwar - Old Trick Threatens the Newest Weapons. New York Times (October 2009)
14. Moradi, A., Kirschbaum, M., Eisenbarth, T., Paar, C.: Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 99, 1-13 (2011)
15. Nangate Inc. Nangate Open Cell Library, version PDKv1 3 v2010 12 (August. 2011), http://www.si2.org/openeda.si2.org/projects/nangatelib
16. Popp, T., Kirschbaum, M., Zefferer, T., Mangard, S.: Evaluation of the Masked Logic Style MDPL on a Prototype Chip. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 81-94. Springer, Heidelberg (2007)
17. Popp, T., Mangard, S.: Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172-186. Springer, Heidelberg (2005)
18. Rajendran, J., Jyothi, V., Karri, R.: Blue team red team approach to hardware trust assessment. In: IEEE 29th International Conference on Computer Design (ICCD 2011), pp. 285-288 (October 2011)
19. Rajendran, J., Jyothi, V., Sinanoglu, O., Karri, R.: Design and analysis of ring oscillator based Design-for-Trust technique. In: 29th IEEE VLSI Test Symposium (VTS 2011), pp. 105-110 (2011)
20. Sanger, D., Barboza, D., Perlroth, N.: Chinese Army Unit Is Seen as Tied to Hacking Against U.S. New York Times (February 2013)
21. Shiyanovskii, Y., Wolff, F., Rajendran, A., Papachristou, C., Weyer, D., Clay, W.: Process reliability based trojans through NBTI and HCI effects. In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2010), pp. 215-222 (2010)
22. SypherMedia International. Circuit Camouflage Technology - SMI IP Protection and Anti-Tamper Technologies. White Paper Version 1.9.8j (March 2012)
23. Waksman, A., Sethumadhavan, S.: Silencing hardware backdoors. In: IEEE Symposium on Security and Privacy (SP 2011), pp. 49-63 (2011)
24. Walker, J.: Conceptual Foundations of the Ivy Bridge Random Number Generator. Presentation at ISTS Computer Science Department Colloquium at Dartmouth College (November 2012), http://www.ists.dartmouth.edu/docs/walker ivy-bridge.pdf
25. Yier, J., Makris, Y.: Hardware Trojan detection using path delay fingerprint. In: IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2008), pp. 51-57 (2008)