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Volumn 1353, Issue , 1997, Pages 111-123

Interactive orthogonal graph drawing: Algorithms and bounds

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS;

EID: 84890124744     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63938-1_55     Document Type: Conference Paper
Times cited : (8)

References (15)
  • 1
    • 85088356890 scopus 로고
    • New Lower Bounds for Orthogonal Graph Drawings
    • Biedl, T.C., New Lower Bounds for Orthogonal Graph Drawings, Proceedings on GD’95, Passau, 28-39, 1995.
    • (1995) Proceedings on GD’95, Passau , pp. 28-39
    • Biedl, T.C.1
  • 5
    • 84957404896 scopus 로고
    • CPLEX Optimization, Inc
    • CPLEX optimization, Inc. Using the CPLEX Base System. CPLEX Optimization, Inc., 1995.
    • (1995)
  • 8
    • 84957570634 scopus 로고
    • On the computational complexity of upward and rectilinear planarity testing
    • Garg, A., R. Tamassia, On the computational complexity of upward and rectilinear planarity testing, Proceedings of GD’94, Princeton, 286-297, 1994.
    • (1994) Proceedings of GD’94, Princeton , pp. 286-297
    • Garg, A.1    Tamassia, R.2
  • 10
    • 0001689774 scopus 로고
    • The complexity of wire routing and finding minimum area layouts for arbitrary VLSI circuits
    • VLSI Theory, Jai Press, Reading, MA
    • Kramer M.R., J. van Leeuwen, The complexity of wire routing and finding minimum area layouts for arbitrary VLSI circuits, Advances in Computer Research, Vol. 2: VLSI Theory, Jai Press, Reading, MA, 129-146, 1992.
    • (1992) Advances in Computer Research , vol.2 , pp. 129-146
    • Kramer, M.R.1    van Leeuwen, J.2
  • 12
    • 84957710112 scopus 로고    scopus 로고
    • Experimental and Theoretical Results in Interactive Orthogonal Graph Drawing
    • Papakostas, A., J. M. Six, I. G. Tollis, Experimental and Theoretical Results in Interactive Orthogonal Graph Drawing, Proceedings on GD’96, Berkeley, 371-386, 1996.
    • (1996) Proceedings on GD’96, Berkeley , pp. 371-386
    • Papakostas, A.1    Six, J.M.2    Tollis, I.G.3
  • 15
    • 0019532794 scopus 로고
    • Universality considerations in VLSI circuits
    • Valiant, L. G., Universality considerations in VLSI circuits, IEEE Trans. Comput., C-30, 135-140, 1981.
    • (1981) IEEE Trans. Comput , vol.C-30 , pp. 135-140
    • Valiant, L.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.