Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2013, Pages 51-52

  Goud, A Arun ^a   Gupta, Sumeet Kumar ^a   Choday, Sri Harsha ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84890053158     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2013.6633788     Document Type: Conference Paper

References (6)

1. K. Roy, et al., DAC '09.
2. RA Vega, et al., IEEE TED, Vol. 56, No. 9, Sep 2009.
3. A. Goel et al., IEEE TED, Vol. 58, No. 2, Feb 2011.
4. S. Steiger, et al., IEEE Transactions on Nanotechnology, Vol. 10, No. 6, Nov 2011.
5. C. Augustine, et al., ISQED 2009
6. M. Staedele, Pro 978-1-4799-0c8e1e4d-i1ng/1s3 o/f 3E1S. S00D ER2C01230 I0E2EE