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Volumn 705 LNCS, Issue , 1993, Pages 199-210

Using FPGAs to implement a reconfigurable highly parallel computer

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT DESIGN; LOGIC GATES; NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS; RECONFIGURABLE HARDWARE;

EID: 84889998095     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-57091-8_45     Document Type: Conference Paper
Times cited : (8)

References (22)
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    • 0024648169 scopus 로고
    • Schemas and neural network for sixth generation computing
    • Arbib, M. A. “Schemas and neural network for sixth generation computing.” Journal of Parallel and Distributed Computing. Vol. 6(2): pp. 185-216, 1989.
    • (1989) Journal of Parallel and Distributed Computing , vol.6 , Issue.2 , pp. 185-216
    • Arbib, M.A.1
  • 5
    • 0009686565 scopus 로고
    • LUCAS Associative Array Processor — Design, P
    • Vol 216 of Lecture Notes in Computer Science. Springer Verlag. Berlin
    • Fernström, C., I. Kruzela and B. Svensson. LUCAS Associative Array Processor — Design, Programming and Application Studies. Vol 216 of Lecture Notes in Computer Science. Springer Verlag. Berlin. 1986.
    • (1986) Rogramming and Application Studies
    • Fernström, C.1    Kruzela, I.2    Svensson, B.3
  • 7
    • 0023855839 scopus 로고
    • An introduction to neural computing
    • Kohonen, T. “An introduction to neural computing.” Neural Networks. Vol. 1: pp. 3-16, 1988.
    • (1988) Neural Networks , vol.1 , pp. 3-16
    • Kohonen, T.1
  • 12
    • 0026827812 scopus 로고
    • Using and designing massively parallel computers for artificial neural networks
    • Nordström, T. and B. Syensson. “Using and designing massively parallel computers for artificial neural networks.” Journal of Parallel and Distributed Computing. Vol. 14(3): pp. 260-285, 1992.
    • (1992) Journal of Parallel and Distributed Computing , vol.14 , Issue.3 , pp. 260-285
    • Nordström, T.1    Syensson, B.2
  • 15
    • 2342487741 scopus 로고
    • A hardware emulator for binary neural networks
    • Paris
    • Skubiszewski, M. “A hardware emulator for binary neural networks.” In International Neural Network Conference, Vol. 2, pp. 555-558, Paris, 1990.
    • (1990) International Neural Network Conference , vol.2 , pp. 555-558
    • Skubiszewski, M.1
  • 17
    • 85029592617 scopus 로고
    • Thinking Machines Corporation, (Version 6.0), T M C Cambridge, Massachusetts
    • Thinking Machines Corporation. “C* User's guide and C* Programming Guide.” (Version 6.0), T M C Cambridge, Massachusetts, 1990.
    • (1990) C* User's Guide and C* Programming Guide


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.