A bias dependent source/drain resistance model in LDD MOSFET devices for distortion analysis

ICVC 1999 - 6th International Conference on VLSI and CAD

Volumn , Issue , 1999, Pages 190-193

  Oh, Kwang Hoon ^a   Yu, Zhiping ^a   Dutton, Robert W ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84889353981     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVC.1999.820870     Document Type: Conference Paper

References (10)

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2. S.L. Jang, S.S Uu, and CJ. Sheu, "A Compact LDD MOSFET I-V Model Based on Nonpinned Surface Potential." IEEE trans. Electron Devices vol.45. no.12. pp. 2489. 1998.
3. P. K. KD. C. HU. et al., BSIM3v3 User's Manual. University of California. Berkeley, 1996.
4. R. Shrivastava, and K. Fitzpatrick. "A simple model for the overlap capacitance of a VLSI MOS device," IEEE trans. Electron Devices vol. ED-29, no. 12, pp. 1870,1982
5. G. S. Huang, and C. Y. Wu, "An analytic I-V model for lightly doped drain (LDD) MOSFET Devices," IEEE trans. Electron De-vicesvol. ED-34,no. 6,pp. 1311, 1987.
6. Y. P. Tsividis. Operation and Modeling of the MOS Transistors. New York; McGraw-Hill. 1988.
7. K. Joardar. K. K. GuUapalli, C. C. McAndiew, M. E. Bumham, and A. Wild, "An Improved MOSFET Model for Circuit Simulation," IEEE Electron Devices, vol. 45, no. 1 pp. 134. 1998.
8. R. van Langevelde, "A Compact MOSFET Model for Distortion Analysis in Analog Circuit Design." Ph.D thesis. Eindhoven University of Technology. 1998.
9. F-S J. Lai. and J. Y-C Sun, "An Analytical One-Dimensional Model for UghUy Doped Drain(LDD) MOSFET Devices," IEEE trans. Electron Devices vol. ED-32. no.12. pp. 2803, 1985.
10. N. Arora, MOSFET Models for VLSI Circuit Simulations-Theory and Practice Springer-Verlag Wien New York, 1993.