Design and Realization of High-Performance Wave-Pipelined 8 x 8 b Multiplier in CMOS Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 3, Issue 1, 1995, Pages 36-48

  Ghosh, Debabrata ^a   Nandy, S K ^b  

^a Texas Instruments ^*  (India)

^b INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

high; High performance multiplier macrocell; multiplier; throughput arithmetic unit; VLSI multipliers; wave pipelined; wave pipelining in CMOS technology

Indexed keywords

EID: 84889152211     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.365452     Document Type: Article

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