Reconfiguration mechanism for an IP block based interconnection

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 42-45

  Kuusilinna, Kimmo ^a   Liimatainen, Pasi ^a   Hamalainen, Timo ^a   Saarinen, Jukka ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

BACKGROUND INFORMATION; IP BLOCK; LOGICAL SIGNALS; LOW-POWER DESIGN; MEMORY STRUCTURE; ON-CHIP INTERCONNECTION; RECONFIGURATION MECHANISMS; VHDL SYNTHESIS;

ELECTRIC POWER SUPPLIES TO APPARATUS;

INFORMATION SCIENCE;

EID: 84889058066     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794443     Document Type: Conference Paper

References (5)

1. P. Conradi, Reuse in Electronic Design. John Wiley &Sons, New York, NY, 1999.
2. J. Hennessy, D. Patterson, Computer Architecture: a Quantitative Approach, 2nd ed. Morgan Kaufmann, San Francisco, CA, 1996.
3. K. Kuusilinna, T. Hämäläinen, P. Liimatainen, J. Saarinen, Low Latency Interconnection for IP-block Based Multimedia Chips. In: G. Gupta, P. Pritchard, H. Shen (ed.). Proc. 2nd IASTED International Conference on Parallel and Distributed Computing and Networks, 1998, pp. 411-416.
4. ANSI/IEEE Std 1076-1993. IEEE Standard VHDL Language Reference Manual. The IEEE. Inc., 1994.
5. PCI Local Bus Specification, Revision 2.1. PCI Special Interest Group, 1995.