PHANTOM: Practical oblivious computation in a secure processor

Proceedings of the ACM Conference on Computer and Communications Security

Volumn , Issue , 2013, Pages 311-324

  Maas, Martin ^a   Love, Eric ^a   Stefanov, Emil ^a   Tiwari, Mohit ^b   Shi, Elaine ^c   Asanović, Krste ^a   Kubiatowicz, John ^a   Song, Dawn ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

Author keywords

fpgas; oblivious ram; path oram; secure processors

Indexed keywords

EMPIRICAL MODEL; HARDWARE IMPLEMENTATIONS; MEMORY CHANNELS; MEMORY CONTROLLER; OFFLOADING COMPUTATIONS; PATH ORAM; SECURE PROCESSORS; STORAGE REQUIREMENTS;

DIGITAL STORAGE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; POPULATION STATISTICS; QUERY LANGUAGES; SECURITY OF DATA;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84889002819     PISSN: 15437221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2508859.2516692     Document Type: Conference Paper

References (42)

1. "PrivateCore," http://www.privatecore.com/.
2. J. Agat, "Transforming out Timing Leaks," in POPL, 2000.
3. A. Askarov, D. Zhang, and A. C. Myers, "Predictive black-box mitigation of timing channels," in CCS, 2010.
4. A. Aviram, S. Hu, B. Ford, and R. Gummadi, "Determinating Timing Channels in Compute Clouds," in CCSW, 2010.
5. J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avizienis, J. Wawrzynek, and K. Asanovic, "Chisel: Constructing Hardware in a Scala Embedded Language," in DAC, 2012.
6. 2 n) overhead," http://arxiv.org/abs/1307.3699, 2013.
7. B. Coppens, I. Verbauwhede, K. D. Bosschere, and B. D. Sutter, "Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors," in SP, 2009.
8. J. Devietti, B. Lucia, L. Ceze, and M. Oskin, "DMP: Deterministic Shared Memory Multiprocessing," in ASPLOS, 2009.
9. C. W. Fletcher, M. v. Dijk, and S. Devadas, "A Secure Processor Architecture for Encrypted Computation on Untrusted Programs," in STC, 2012.
10. C. Gentry, K. Goldman, S. Halevi, C. Julta, M. Raykova, and D. Wichs, "Optimizing oram and using it efficiently for secure computation," in PETS, 2013.
11. O. Goldreich, "Towards a Theory of Software Protection and Simulation by Oblivious RAMs," in STOC, 1987.
12. O. Goldreich and R. Ostrovsky, "Software Protection and Simulation on Oblivious RAMs," J. ACM, 1996.
13. M. T. Goodrich and M. Mitzenmacher, "Privacy-Preserving Access of Outsourced Data via Oblivious RAM Simulation," in ICALP, 2011.
14. M. T. Goodrich, M. Mitzenmacher, O. Ohrimenko, and R. Tamassia, "Privacy-preserving Group Data Access via Stateless Oblivious RAM Simulation," in SODA, 2012.
15. Y. Gu, Y. Fu, A. Prakash, Z. Lin, and H. Yin, "OS-Sommelier: Memory-only Operating System Fingerprinting in the Cloud," in SoCC, 2012.
16. A. Haeberlen, B. C. Pierce, and A. Narayan, "Differential Privacy Under Fire," in USENIX Security, 2011.
17. J. A. Halderman, S. D. Schoen, N. Heninger, W. Clarkson, W. Paul, J. A. Calandrino, A. J. Feldman, J. Appelbaum, and E. W. Felten, "Lest We Remember: Cold-boot Attacks on Encryption Keys," Commun. ACM, vol. 52, no. 5, 2009.
18. A. Hodjat and I. Verbauwhede, "A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA," in FCCM, 2004.
19. A. Huang, "Keeping Secrets in Hardware: The Microsoft Xbox Case Study," in CHES, 2002.
20. G. Klein, K. Elphinstone, G. Heiser, J. Andronick, D. Cock, P. Derrin, D. Elkaduwe, K. Engelhardt, R. Kolanski, M. Norrish, T. Sewell, H. Tuch, and S. Winwood, "seL4: Formal Verification of an OS Kernel," in SOSP, 2009.
21. E. Kushilevitz, S. Lu, and R. Ostrovsky, "On the (In)security of Hash-based Oblivious RAM and a New Balancing Scheme," in SODA, 2012.
22. J. R. Lorch and B. Parno, "Shroud: Ensuring Private Access to Large-Scale Data in the Data Center," in FAST, 2013.
23. R. Martin, J. Demme, and S. Sethumadhavan, "TimeWarp: Rethinking Timekeeping and Performance Monitoring Mechanisms to Mitigate Side-channel Attacks," in ISCA, 2012.
24. R. Ostrovsky and V. Shoup, "Private Information Storage (Extended Abstract)," in STOC, 1997.
25. L. Ren, C. Fletcher, X. Yu, M. van Dijk, and S. Devadas, "Integrity verification for path oblivious-ram," in HPEC, 2013.
26. L. Ren, X. Yu, C. W. Fletcher, M. van Dijk, and S. Devadas, "Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors," in ISCA, 2013.
27. B. Rogers, S. Chhabra, M. Prvulovic, and Y. Solihin, "Using address independent seed encryption and bonsai merkle trees to make secure processors os- and performance-friendly," in MICRO, 2007.
28. 3) Worst-Case Cost," in ASIACRYPT, 2011.
29. S. W. Smith, "Outbound Authentication for Programmable Secure Coprocessors," in ESORICS, 2002.
30. E. Stefanov and E. Shi, "Oblivistore: High performance oblivious cloud storage," in S & P, 2013.
31. E. Stefanov, E. Shi, and D. Song, "Towards Practical Oblivious RAM," in NDSS, 2012.
32. E. Stefanov, M. van Dijk, E. Shi, C. Fletcher, L. Ren, X. Yu, and S. Devadas, "Path O-RAM: An Extremely Simple Oblivious RAM Protocol," in CCS, 2013.
33. G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, "AEGIS: Architecture for Tamper-evident and Tamper-resistant Processing," in ICS, 2003.
34. D. L. C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell, and M. Horowitz, "Architectural Support for Copy and Tamper Resistant Software," SIGOPS Oper. Syst. Rev., vol. 34, no. 5, pp. 168-177, 2000.
35. M. Tiwari, H. M. Wassel, B. Mazloom, S. Mysore, F. T. Chong, and T. Sherwood, "Complete Information Flow Tracking from the Gates up," in ASPLOS, 2009.
36. A. Waksman and S. Sethumadhavan, "Silencing Hardware Backdoors," in SP, 2011.
37. A. Waterman, Y. Lee, D. A. Patterson, and K. Asanović, "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA," EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62, May 2011.
38. P. Williams and R. Sion, "Round-Optimal Access Privacy on Outsourced Storage," in CCS, 2012.
39. P. Williams, R. Sion, and B. Carbunar, "Building castles out of mud: practical access pattern privacy and correctness on untrusted storage," in CCS, 2008.
40. P. Williams, R. Sion, and A. Tomescu, "PrivateFS: A Parallel Oblivious File System," in CCS, 2012.
41. D. Zhang, A. Askarov, and A. C. Myers, "Predictive Mitigation of Timing Channels in Interactive Systems," in CCS, 2011.
42. X. Zhuang, T. Zhang, and S. Pande, "HIDE: An Infrastructure for Efficiently Protecting Information Leakage on the Address Bus," in ASPLOS, 2004.