FPGA realization of RNS to binary signed conversion architecture

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 350-353

  Re, Marco ^a   Nannarelli, Alberto ^a   Cardarilli, Giaiz Carlo ^a   Lojacono, Roberto ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC ARCHITECTURES; CONVERSION PROCEDURES; MODULI SETS; MULTIMEDIA APPLICATIONS; RESIDUAL ARITHMETIC; RESIDUE NUMBER SYSTEM; SIGNED NUMBERS;

NUMBERING SYSTEMS;

ALGORITHMS;

EID: 84888042603     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922245     Document Type: Conference Paper

References (14)

1. M. Bhardwaj and A. Balaram, "Low Power Signal Processing Architectures Using Residue Arithmetic," Proceedings of IEEE International Conference on Acoustic, Speech and Signal Processing (ASSP'98), vol. 5, pp. 3017-3020, 1998.
2. G. C. Cardarilli, A. Nannarelli and Marco Re, "Reducing Power Dissipation in FIR Filters using the Residue Number System," Midwest Symposium on Circuit and Systems 2000, Lansing, Michigan, Augut 8-11, 2000.
3. R. Conway, J. Nelson, "Fast Converter for 3 Moduli RNS Using New Property of CRT," IEEE Trans, on Computers, Vol. 48, no. 8, pp. 852-860, August 1999.
4. D. Gallaher, F. E. Petty, and P. Srinivasan, " The Digit Parallel Method for Fast RNS to Weighted Number System Conversion for Speci'c Moduli (2fc-l, 2fc, 2fc+l," IEEE Trans. Circuits Syst.-II, Vol. 44, no. 1, pp. 53-57, January 1997.
5. S. K. Mitra, J. F. Kaiser,"Handbook for Digital Signal Processing," Chapter 9, pp. 611-677, John Wiley & Sons.
6. S. Piestrak, "A High-Speed Realization of a Residue to Binary Number System Converter," IEEE Trans. Circuits Syst.-II, Vol. 42, no. 10, pp. 661-663, October 1995.
7. A. B. Premkumar, "An RNS to Binary Converter in 2n-l, 2n, 2n+l Moduli Set," IEEE Trans. Circuits Syst.-II, Vol. 39, no. 7, pp. 480-482, July 1992.
8. A. B. Premkumar, M. Bhardwaj, and T. Srikathan, "High-Speed and Low-Cost Reverse Converters for die 2n - 1, 2n, 2n + 1 Moduli Set," IEEE Trans. Circuits Syst.-II, Vol. 45, no. 7, pp. 903-908, July 1998.
9. K.M. Elleyth, M.A. Bayoumi, "Fast and Flexible Architectures for RNS Arithmetic Decoding," IEEE Trans.Circuits Systems.-II Analog and Digital Signal Processing, Vol.39, No.4, pp. 226-235, April 1992.
10. F. Barsi, "Mod m arithmetic in binary systems," Information Processing Letters, Vol.40, No.6, pp. 303-309, 30 December 1991.
11. W.L.Freking, K.K.Parhi, "Low-Power Digital Filters Using Residue Arithmetic," Thirthy-First Asilomar Conference on Signals, Systems and Computers 1998, Vol. 1, pp.739-743, 1998.
12. G.Cardarilli, M. Re, R.Lojacono," A Residue to Binary Conversion Algorithm for Signed Numbers," European Conference on Circuit Theory and Design ECCTD '97, Vol. 3, pp. 1456-1459, 31 August-3 September 1997, Budapest, Hungary.
13. N.S. Szabo and R.I. Tanaka, "Residue Arithmetic and its Applications in Computer Technology," New York: McGraw-Hill, 1967.
14. M.A. Sodestrand, W.K. Jenkins, G. A. Jullien, F. J. Taylor, "Residue Number System Arithmetic: Modern Applications in Digital Signal Processing," New York: IEEE Press, 1986.