A hardware design approach for merge-sorting network

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 534-537

  Huang, Chun Yueh ^a   Yu, Gwo Jeng ^b   Liu, Bin Da ^b  

^a KUNG SHAN INSTITUTE OF TECHNOLOGY   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA MEMORY; FIXED SIZE; HARDWARE DESIGN; HARDWARE FABRICATION; MEMORY ADDRESSING CONTROLLERS; PARALLEL SORTING; SORTING NETWORK; VERILOG VHDL;

COMPLEX NETWORKS; DATA TRANSFER; HARDWARE;

SORTING;

EID: 84887927234     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922292     Document Type: Conference Paper

References (6)

1. P. Zhou and O. W. W. Yang, "A new design of central queueing ATM switches," IEEE Global Telecommunications Conf. GLOBECOM '97, pp. 541-545, vol.1, 1997
2. C. C. Lin and C. J. Kuo, "Two dimensional rank-order filter by using max-min sorting network," IEEE Trans. Circuit and Syst. for Vedio Technology, vol.8, no.8,pp. 941-946, Dec. 1998.
3. K. E. Batcher, "Sorting networks and their applications," Proc. AFIPS Conf, pp.307-314, 1968.
4. D. L. Lee and K. E. Batcher, "A multiway merge sorting network." IEEE Trans. Parallel and Distributed Syst., vol.6, no.2 pp. 211-215, Feb. 1995.
5. T. Nakatani, S. T. Huang, B. W. Arden and S. K. Tripathi, "K-way bitonic sort," IEEE Trans. Computers, vol.38, no.2 pp.283-288, Feb. 1989.
6. S. Olariu, M. C. Pinotti, and S. Q. Zheng, "How to sort N items using a sorting network of fixed I/O size," IEEE Trans. Parallel and Distributed Syst., vol.10, no.5 pp. 487-499, May 1999.