Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations

IEEE Transactions on Parallel and Distributed Systems

Volumn 24, Issue 12, 2013, Pages 2451-2461

  Carrillo, Snaider ^a   Harkin, Jim ^a   McDaid, Liam J ^a   Morgan, Fearghal ^b   Pande, Sandeep ^b   Cawley, Seamus ^b   McGinley, Brian ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b NATIONAL UNIVERSITY OF IRELAND   (Ireland)

Author keywords

Interconnection architecture; Network on chip; Neurocomputers; Real time distributed; Spiking neural networks

Indexed keywords

INTERCONNECTION ARCHITECTURE; NETWORK ON CHIP; NEUROCOMPUTERS; REAL-TIME DISTRIBUTED; SPIKING NEURAL NETWORKS;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA PROCESSING; HARDWARE; INTELLIGENT AGENTS; LOW POWER ELECTRONICS; MAMMALS; NETWORK ARCHITECTURE; NEURONS; ROUTERS; SCALABILITY; SERVERS; VLSI CIRCUITS;

NEURAL NETWORKS;

EID: 84887917957     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2012.289     Document Type: Article

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