Chip/package mechanical stress impact on 3-D IC reliability and mobility variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 11, 2013, Pages 1694-1707

  Jung, Moongon ^a   Pan, David Z ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

3 D IC; chip package co analysis; full stack timing; mechanical reliability; stress; TSV

Indexed keywords

CO-ANALYSIS; FINITE ELEMENT ANALYSIS METHOD; FULL-STACK TIMING; LINEAR SUPERPOSITIONS; MECHANICAL RELIABILITY; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA (TSV); TSV;

INTEGRATED CIRCUITS; RELIABILITY ANALYSIS; TOOLS;

STRESSES;

EID: 84886679416     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2013.2265372     Document Type: Article

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