Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 669-672

  Park, M H ^a   Hong, S H ^a   Hong, S J ^a   Park, T ^a   Song, S ^a   Park, J H ^a   Kim, H S ^a   Shin, Y G ^a   Kang, H K ^a   Lee, M Y ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION (PECVD); SHALLOW TRENCH ISOLATION (STI);

CHEMICAL VAPOR DEPOSITION; DEFECTS; DENSIFICATION; MOSFET DEVICES; OXIDES; PLASMA APPLICATIONS; STRESS ANALYSIS; TENSILE PROPERTIES;

CMOS INTEGRATED CIRCUITS;

EID: 84886448045     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)