Application of process synthesis methodology for first-pass fabrication success of high-performance deep-submicron CMOS

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 149-152

  Saxena, Sharad ^a   Burch, Richard ^a   Vasanth, Karthik ^a   Rao, Suraj ^a   Fernando, Chenjing ^a   Davis, Joseph ^a   Mozumder, P K ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESS SYNTHESIS METHODOLOGY;

ALGORITHMS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING;

CMOS INTEGRATED CIRCUITS;

EID: 84886448044     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)