Fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 851-854

  Lin, T ^a   Chen, C ^a   Hsu, S Y ^a   Tsai, M J ^a   Yew, T R ^a   Chou, J W ^a   Haung, K T ^a   Wu, J Y ^a   Ku, Y C ^a   Liu, C C ^a   Yang, M S ^a   Yeh, W K ^a   Huang, C H ^a   Lur, W ^a   Huang, H S ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MICRON FOUNDRY MANUFACTURING; STATIC RANDOM ACCESS MEMORY (SRAM);

GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 84886447985     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)