Model checking through symbolic reachability graph

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1214, Issue , 1997, Pages 213-224

  Ilié, Jean Michel ^a,b   Ajami, Khalil ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

^b UNIVERSITÉ PARIS DESCARTES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

SOFTWARE DESIGN; SPECIFICATIONS;

CONDENSED REPRESENTATIONS; FORMAL CHECKING; SYMBOLIC REACHABILITY; SYSTEM STATE;

MODEL CHECKING;

EID: 84885711014     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0030598     Document Type: Conference Paper

References (7)

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3. G. Chiota, R. Gaeta, "Efficient Simulation of Parallel Architectures Exploiting Symmetric Well-formed Petri Net Models", 6th International Workshop on Petri, nets and Performance Models, Durham, NC, USA, October 1995.
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5. E. Clarke, O. Grumberg, D. Long, "Verification Tools for Finite-State Concurrear Systems", "A Decade of Concurrency - Reflections and Perspectives", LNCS vol 803, 1994.
6. S. Haddad, JM. Ili6, B. Zouari, M. Taghelit, "Symbolic Reachability Graph and Partial Symmetries", In Proc. of the 16th International Conference on Application and Theory of Petri Nets, pp 238-257, Torino, Italy, June 1995.
7. Z. Manna, A. Pnueli. "The temporal Logic of Reactive and Concurrent Systems: Specification", Springer-Verlag,1992.