메뉴 건너뛰기




Volumn , Issue , 2013, Pages 194-197

Multi-pumping for resource reduction in FPGA high-level synthesis

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PUMPS;

EID: 84885667952     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.053     Document Type: Conference Paper
Times cited : (31)

References (16)
  • 1
    • 84885580140 scopus 로고    scopus 로고
    • Altera, Corp., San Jose, CA
    • Altera, Corp., San Jose, CA. DE4 Development Board, 2010.
    • (2010) DE4 Development Board
  • 2
    • 84885602611 scopus 로고    scopus 로고
    • Altera, Corp., San Jose, CA
    • Altera, Corp., San Jose, CA. Stratix-IV Data Sheet, 2010.
    • (2010) Stratix-IV Data Sheet
  • 7
    • 34547187799 scopus 로고    scopus 로고
    • An efficient and versatile scheduling algorithm based on sdc formulation
    • J. Cong and Z. Zhang. An efficient and versatile scheduling algorithm based on sdc formulation. In Design Automation Conference, pages 433-438, 2006.
    • (2006) Design Automation Conference , pp. 433-438
    • Cong, J.1    Zhang, Z.2
  • 12
    • 77952743988 scopus 로고    scopus 로고
    • JEDEC Solid State Technology Assoc.
    • JEDEC Solid State Technology Assoc. DDR3 SDRAM Standard (JESD 79-3B), 2008.
    • (2008) DDR3 SDRAM Standard (JESD 79-3B)
  • 14
    • 0023230724 scopus 로고
    • Force-directed scheduling in automatic data path synthesis
    • P. G. Paulin and J. P. Knight. Force-directed scheduling in automatic data path synthesis. In ACM/IEEE Design Automation Conf., pages 195-202, 1987.
    • (1987) ACM/IEEE Design Automation Conf. , pp. 195-202
    • Paulin, P.G.1    Knight, J.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.