메뉴 건너뛰기




Volumn , Issue , 2013, Pages 1579-1582

Compiling control-intensive loops for CGRAs with state-based full predication

Author keywords

CGRA; Compilation; Conditional; Predicated execution; Predication; Reconfigurable architecture

Indexed keywords

CONFORMAL MAPPING; DATA TRANSFER;

EID: 84885631298     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.321     Document Type: Conference Paper
Times cited : (18)

References (19)
  • 1
    • 0026964221 scopus 로고
    • A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high speed DSP data paths
    • dec
    • D. Chen and J. Rabaey, "A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high speed DSP data paths," IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1895-1904, dec 1992.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , pp. 1895-1904
    • Chen, D.1    Rabaey, J.2
  • 3
    • 0034187952 scopus 로고    scopus 로고
    • MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
    • may
    • H. Singh, M. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and M. C. Filho, "MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications," IEEE Transactions on Computers, Vol. 49, pp. 465-481, may 2000.
    • (2000) IEEE Transactions on Computers , vol.49 , pp. 465-481
    • Singh, H.1    Lee, M.2    Lu, G.3    Kurdahi, F.J.4    Bagherzadeh, N.5    Filho, M.C.6
  • 19
    • 84885676243 scopus 로고    scopus 로고
    • http://clang.llvm.org/.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.