Identifying the sources of unpredictability in COTS-based multicore systems

Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013

Volumn , Issue , 2013, Pages 39-48

  Dasari, Dakshina ^a   Akesson, Benny ^a   Nélis, Vincent ^a   Awan, Muhammad Ali ^a   Petters, Stefan M ^a  

^a POLYTECHNIC INSTITUTE OF PORTO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL FEATURES; COMPUTATIONAL CAPABILITY; EMBEDDED APPLICATION; FUNCTIONAL BEHAVIORS; HARDWARE RESOURCES; LOW-POWER CONSUMPTION; REAL TIME REQUIREMENT; SMALL FORM FACTORS;

REAL TIME SYSTEMS;

EMBEDDED SYSTEMS;

EID: 84885416097     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIES.2013.6601469     Document Type: Conference Paper

References (82)

1. V. Tran, D.-B. Liu, and B. Hummel, "Component-based systems development: challenges and lessons learned," in Software Technology and Engineering Practice, 1997. Proceedings., Eighth IEEE International Workshop on [incorporating Computer Aided Software Engineering], jul 1997, pp. 452-462.
2. C. Watkins and R. Walter, "Transitioning from federated avionics architectures to integrated modular avionics," in 26th IEEE/AIAA Digital Avionics Systems Conference (DASC), October 2007, pp. 2.A.1-1-2.A.1-10.
3. M. Di Natale and A. Sangiovanni-Vincentelli, "Moving from federated to integrated architectures in automotive: The role of standards, methods and tools," Proceedings of the IEEE, vol. 98, no. 4, pp. 603-620, April 2010.
4. J. Child, Multicore Processing Becomes the New Mainstream. [Online]. Available: http://www.cotsjournalonline.com/articles/view/101319
5. A. H. R. Albers, E. A. L. Suijs, and P. H. N. De, " Memorycommunication model for low-latency x-ray video processing on multiple cores."
6. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. B. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. P. Puschner, J. Staschulat, and P. Stenström, "The worst-case execution time problem - overview of methods and survey of tools," ACM Transactions on Embedded Computing Systems, vol. 7, no. 3, 2008.
7. S. Mohan, M. Caccamo, L. Sha, R. Pellizzoni, G. Arundale, R. Kegley, and D. de Niz, "Using multicore architectures in cyber-physical systems," Workshop on Developing Dependable and Secure Automotive Cyber-Physical Systems from Components., 2011.
8. C. Ferdinand, R. Heckmann, and B. Franzen, "Static memory and timing analysis of embedded systems code," in Proceedings of VVSS2007 - 3rd European Symposium on Verification and Validation of Software Systems, 23rd of March 2007, Eindhoven, P. Groot, Ed., 2007. [Online]. Available: http://www-fp.cs.st-andrews.ac.uk/embounded/pubs/papers/VVSS07.pdf
9. A. Ermedahl, A Modular Tool Architecture for Worst-Case Execution-Time Analysis. VDM Verlag, 2008.
10. Rapita Systems Ltd., "Rapitime explained," Rapita Systems Ltd., http://www.rapitasystems.com/downloads/rapitime explained white paper".
11. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 966-978, July 2009.
12. R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, "The influence of processor architecture on the design and the results of wcet tools," Proceedings of the IEEE, vol. 91, no. 7, pp. 1038-1054, july 2003.
13. L. Thiele and R. Wilhelm, "Design for time-predictability," in Design of Systems with Predictable Behaviour, 2004.
14. S. Basumallick and K. Nilsen, "Cache issues in real-time systems," 1994.
15. D. Grund, "Static cache analysis for real-time systems - LRU, FIFO, PLRU," Ph.D. dissertation, 2012. [Online]. Available: https://www.epubli. de/shop/buch/Static-Cache-Analysis-for-Real-Time-Systems-Daniel-Grund- 9783844216998/13092
16. H. Ramaprasad and F. Mueller, "Tightening the bounds on feasible preemptions," ACM Trans. Embed. Comput. Syst., vol. 10, no. 2, pp. 27:1-27:34, Jan. 2011.
17. C. Ferdinand and R. Wilhelm, "Efficient and precise cache behavior prediction for real-time systems," Real-Time Systems, vol. 17, pp. 131-181, 1999.
18. Intel 4 Series Chipset Family Datasheet, For the Intel 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 Graphics and Memory Controller Hub (GMCH) and the Intel® 82P45, 82P43 Memory Controller Hub (MCH), Intel Corporation, 2010.
19. J. Reineke, D. Grund, C. Berg, and R. Wilhelm, "Timing predictability of cache replacement policies," Real-Time Systems, vol. 37, no. 2, pp. 99-122, Nov. 2007.
20. J. Yan and W. Zhang, "WCET analysis for multi-core processors with shared L2 instruction caches," in RTAS'08: Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium, 2008, pp. 80-89.
21. Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury, "Timing analysis of concurrent programs running on shared cache multi-cores," in Proc. of IEEE Real-Time Systems Symposium, 2009.
22. J. M. Calandrino and J. H. Anderson, "Cache-aware real-time scheduling on multicore platforms: Heuristics and a case study," in ECRTS, 2008, pp. 299-308.
23. S. Cho, L. Jin, and K. Lee, "Achieving predictable performance with on-chip shared l2 caches for manycore-based real-time systems," in Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2007, pp. 3-11.
24. V. Suhendra and T. Mitra, "Exploring locking & partitioning for predictable shared caches on multi-cores," in DAC'08: Proceedings of the 45th annual Design Automation Conference. ACM, 2008, pp. 300-303.
25. N. Guan, M. Stigge, W. Yi, and G. Yu, "Cache-aware scheduling and analysis for multicores," in EMSOFT'09: Proceedings of the seventh ACM international conference on Embedded software, 2009, pp. 245-254.
26. G. Taylor, P. Davies, and M. Farmwald, "The tlb slice-a low-cost highspeed address translation mechanism," in ISCA'90: Proceedings of the 17th annual international symposium on Computer Architecture. ACM, 1990, pp. 355-363.
27. D. Hardy, T. Piquet, and I. Puaut, "Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches," in RTSS'09: Proceedings of the 2009 30th IEEE Real-Time Systems Symposium, 2009, pp. 68-77.
28. ISO26262-4, Road vehicles - Functional safety - Part 4: Product development at the system level, 1st ed., 2011.
29. ISO26262-1, Road vehicles - Functional safety - Part 1: Vocabulary, 1st ed., 2011.
30. IEC 61508, Functional safety of electrical/electronic/programmable electronic safety-related systems, 2010.
31. S. Zhuravlev, S. Blagodurov, and A. Fedorova, "Addressing shared resource contention in multicore processors via scheduling," SIGPLAN Not., vol. 45, no. 3, pp. 129-142, 2010.
32. S. Chattopadhyay, A. Roychoudhury, and T. Mitra, "Modeling shared cache and bus in multicores for timing analysis," in Proceedings of the 13th International Workshop on Software Compilers for Embedded Systems, 2010, pp. 6:1-6:10.
33. A. Schranzhofer, J.-J. Chen, and L. Thiele, "Timing analysis for TDMA arbitration in resource sharing systems," in Proceedings of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, 2010, pp. 215-224.
34. A. Schranzhofer, R. Pellizzoni, J.-J. Chen, L. Thiele, and M. Caccamo, "Timing analysis for resource access interference on adaptive resource arbiters," in Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011, pp. 213-222.
35. T. Kelter, H. Falk, P. Marwedel, S. Chattopadhyay, and A. Roychoudhury, "Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds," in Proceedings of the 2011 Euromicro Conference on Real-Time Systems, 2011, pp. 3-12.
36. J. Rosen, A. Andrei, P. Eles, and Z. Peng, "Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip," in RTSS'07: Proceedings of the 28th IEEE International Real-Time Systems Symposium, 2007, pp. 49-60.
37. S. Schliecker, M. Negrean, and R. Ernst, "Bounding the shared resource load for the performance analysis of multiprocessor systems," in Proceedings of the Conference on Design, Automation and Test in Europe, 2010, pp. 759-764.
38. R. Pellizzoni, A. Schranzhofer, J. J. Chen, M. Caccamo, and L. Thiele, "Worst case delay analysis for memory interference in multicore systems," in Proceedings of Design, Automation, and Test in Europe, 2010, pp. 741-746.
39. D. Dasari, B. Andersson, V. Nelis, S. M. Petters, A. Easwaran, and J. Lee, "Response time analysis of COTS-based multicores considering the contention on the shared memory bus," in IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications, nov. 2011, pp. 1068-1075.
40. D. Dasari and V. Nelis, "An analysis of the impact of bus contention on the wcet in multicores," in IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), june 2012, pp. 1450-1457.
41. W. Yi, "Multicore Embedded Systems: The Timing Problem and Possible Solutions," in ICFEM, 2010, pp. 22-23.
42. A. Gustavsson, A. Ermedahl, B. Lisper, and P. Pettersson, "Towards WCET analysis of multicore architectures using UPPAAL," in WCET, 2010, pp. 101-112.
43. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, "Memory access control in multiprocessor for real-time systems with mixed criticality," in Real-Time Systems (ECRTS), 2012 24th Euromicro Conference on, july 2012, pp. 299-308.
44. DDR3 SDRAM Specification, JESD79-3E ed., JEDEC Solid State Technology Association, Jul. 2010.
45. B. Jacob, N. G. Spencer, and D. Wang, Memory Systems Cache, DRAM, Disk. Morgan Kaufmann, 2007, pp. 497-520.
46. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, "Memory access scheduling," in ISCA'00: Proceedings of the 27th annual international symposium on Computer architecture, 2000, pp. 128-138.
47. B. Akesson and K. Goossens, "Architectures and modeling of predictable memory controllers for improved system integration," in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, 2011, pp. 1-6.
48. M. Paolieri, E. Quinones, F. Cazorla, and M. Valero, "An Analyzable Memory Controller for Hard Real-Time CMPs," Embedded Systems Letters, IEEE, vol. 1, no. 4, pp. 86-90, 2009.
49. J. Reineke, I. Liu, H. Patel, S. Kim, and E. A. Lee, "PRET DRAM Controller: Bank Privatization for Predictability and Temporal Isolation," in CODES+ISSS'11: Proceedings of the IEEE/ACM international conference on Hardware/software codesign and system synthesis, Oct. 2011, pp. 99-108.
50. J. Dodd, "Adaptive page management," Jul. 2006, uS Patent 7,076,617.
51. S. Goossens, B. Akesson, and K. Goossens, "Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers," in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2013, pp. 525-530.
52. O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers," IEEE Micro, vol. 29, no. 1, pp. 22-32, 2009.
53. J. Shao and B. Davis, "A burst scheduling access reordering mechanism," in Proceedings of the 13th International Symposium on High-Performance Computer Architecture, 2007, pp. 285-294.
54. S. Heithecker and R. Ernst, "Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements," 2005, pp. 575-578.
55. S. Whitty and R. Ernst, "A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture," in Proceedings of the Parallel and Distributed Processing Symposium (IPDPS), 2008.
56. A. Burchard, E. Hekstra-Nowacka, and A. Chauhan, "A real-time streaming memory controller," in Proc. of Design, Automation and Test in Europe Conference, 2005, pp. 20-25.
57. C. Macian, S. Dharmapurikar, and J. Lockwood, "Beyond performance: Secure and fair memory management for multiple systems on a chip," in IEEE International Conference on Field-Programmable Technology (FPT), 2003, pp. 348-351.
58. W.-D. Weber, Efficient Shared DRAM Subsystems for SOCs, Sonics, Inc, 2001, white paper.
59. K. Lee, T. Lin, and C. Jen, "An efficient quality-aware memory controller for multimedia platform SoC," vol. 15, no. 5, pp. 620-633, 2005.
60. S. Novak, J. Peck Jr, and S. Waldron, "Method and apparatus for optimizing memory performance with opportunistic refreshing," Nov. 2000, uS Patent 6,147,921.
61. S. Biswas, "Refresh-ahead and burst refresh preemption technique for managing dram in computer system," May 1999, uS Patent 5,907,857.
62. E. Gerchman, M. Gildea, W. Hovis, R. Jensen, W. Maule, T. Osten, and A. Wottreng, "System and method for memory self-timed refresh for reduced power consumption," Dec. 2001, uS Patent 6,334,167.
63. V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. Irwin, "Hardware and software techniques for controlling dram power modes," Computers, IEEE Transactions on, vol. 50, no. 11, pp. 1154-1173, 2001.
64. G. Thomas, K. Chandrasekar, B. Akesson, B. Juurlink, and K. Goossens, "A predictor-based power-saving policy for dram memories," in Proceedings of 15th Euromicro Conference on Digital System Design (DSD), 2012.
65. http://www.acpi.info/, Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba.
66. Desktop 3rd Generation IntelCore Processor Family Datasheet Volume 1 of 2, Intel Corp.
67. Thermal Mechanical Specifications and Design Guidelines (TMSDG), Intel Corp.
68. F. Gruian, "System-level design methods for low-energy architectures containing variable voltage processors," in Proceedings of the 1st International Workshop on Power-Aware Computer Systems-Revised Papers. Springer-Verlag, 2001, pp. 1-12.
69. Y. Zhang, X. S. Hu, and D. Z. Chen, "Task scheduling and voltage selection for energy minimization," in Proceedings of the 39th annual Design Automation Conference, ser. DAC'02. ACM, 2002, pp. 183-188.
70. R. Mishra, N. Rastogi, D. Zhu, D. Mossé, and R. Melhem, "Energy aware scheduling for distributed real-time systems," in Proceedings of the 17th International Symposium on Parallel and Distributed Processing, ser. IPDPS'03. IEEE Computer Society, 2003, pp. 21.2-.
71. J.-J. Chen, H.-R. Hsu, K.-H. Chuang, C.-L. Yang, A.-C. Pang, and T.-W. Kuo, "Multiprocessor energy-efficient scheduling with task migration considerations," in Proceedings of the 16th Euromicro Conference on Real-Time Systems, ser. ECRTS'04. IEEE Computer Society, 2004, pp. 101-108.
72. J.-J. Chen, H.-R. Hsu, and T.-W. Kuo, "Leakage-aware energy-efficient scheduling of real-time tasks in multiprocessor systems," in Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium, ser. RTAS'06. IEEE Computer Society, 2006, pp. 408-417.
73. J.-J. Chen and C.-F. Kuo, "Energy-efficient scheduling for real-time systems on dynamic voltage scaling (dvs) platforms," in Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, ser. RTCSA'07. IEEE Computer Society, 2007, pp. 28-38.
74. V. Nélis, J. Goossens, R. Devillers, D. Milojevic, and N. Navet, "Poweraware real-time scheduling upon identical multiprocessor platforms," in SUTC'08: Proceedings of the 2008 IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing, 2008, pp. 209-216.
75. V. Nelis and J. Goossens, "Mora: An energy-aware slack reclamation scheme for scheduling sporadic real-time tasks upon multiprocessor platforms," in Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, ser. RTCSA'09, 2009, pp. 210-215.
76. T. Chantem, R. P. Dick, and X. S. Hu, "Temperature-aware scheduling and assignment for hard real-time applications on mpsocs," in Proceedings of the conference on Design, automation and test in Europe, ser. DATE'08. ACM, 2008, pp. 288-293.
77. N. Fisher, J.-J. Chen, S. Wang, and L. Thiele, "Thermal-aware global real-time scheduling on multicore systems," in Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications, ser. RTAS'09. IEEE Computer Society, 2009, pp. 131-140.
78. W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Thermal-aware task allocation and scheduling for embedded systems," in Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, ser. DATE'05. IEEE Computer Society, 2005, pp. 898-899.
79. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G. De Micheli, "Temperature-aware processor frequency assignment for mpsocs using convex optimization," in Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, 2007, pp. 111-116.
80. B. B. Brandenburg, H. Leontyev, and J. H. Anderson, "Accounting for interrupts in multiprocessor real-time systems," 2009.
81. M. Bennett and N. Audsley, "Predictable and efficient virtual addressing for safety-critical real-time systems," in Real-Time Systems, 13th Euromicro Conference on, 2001, pp. 183-190.
82. Optimizing Application Performance on Intel Core Microarchitecture Using Hardware-Implemented Prefetchers. [Online]. Available: http://software.intel. com/en-us/articles/optimizingapplication-performance-on-intel-coret- microarchitecture-usinghardware-implemented-prefetchers